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Patent US4121165A successfully refreshed from Google Patents.
US4121165A
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Digital demodulator with interpolation for linearly amplitude-modulated data signals
Assignee: Telecom Italia SpA
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Filing: 1977-04-22
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Granted: 1978-10-17
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Expires: 1997-04-22
Abstract
Abstract A digital demodulator of data signals transmitted by linear amplitude modulation of a carrier, sampled under the control of clock pulses CK1, comprises an interpolating unit UIN including a tapped delay line TDL whose outputs carry, at a given instant, respective signal samples received during different clock cycles. These signal samples are fed to a transversal filter FIN also receiving two sets of interpolation coefficients a k , b k read out from respective memory sections ME1, ME2. The signal samples from the several delay-line taps are multiplied in filter FIN by the two sets of coefficients a k and b k , under the control of a pulse train CK2 and another pulse train CK3 of the same cadence but phase-shifted with reference to the former, and the two sets of resulting products are respectively summed in a digital adder SM and alternately read out to a phase corrector CJ recovering the phase coherence of the demodulated baseband signal.
Inventors
- 👤 Renato Dogliotti
- 👤 Umberto Mazzei
- 👤 Umberto Mengali
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 09:46
CPC Classifications
H; H04; H04L; H04L27/00; H04L27/02; H04L27/06
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
170 words
A digital demodulator of data signals of a given symbol frequency transmitted by linear amplitude modulation of a carrier, comprising: a source of first, second and third clock pulses, said first clock pulses having a cadence higher than said symbol frequency but not harmonically related thereto, said second and third clock pulses having a cadence equal to said symbol frequency while being relatively staggered by half a cycle of their cadence; analog/digital conversion means connected to said source for deriving a series of digitized samples from an incoming modulated carrier at the cadence of said first clock pulses; delay means connected to said conversion means and controlled by said first clock pulses for simultaneously presenting a multiplicity of successively received digitized samples on respective outputs thereof; first and second memory means respectively storing first and second sets of interpolation coefficients which are functions of the carrier frequency, said first and second memory means having enabling inputs connected to said source for respectively receiving said second and third clock pulses therefrom;
Claim 2
Dependent Claim
170 words
A digital demodulator of data signals of a given symbol frequency transmitted by linear amplitude modulation of a carrier, comprising: a source of first, second and third clock pulses, said first clock pulses having a cadence higher than said symbol frequency but not harmonically related thereto, said second and third clock pulses having a cadence equal to said symbol frequency while being relatively staggered by half a cycle of their cadence; analog/digital conversion means connected to said source for deriving a series of digitized samples from an incoming modulated carrier at the cadence of said first clock pulses; delay means connected to said conversion means and controlled by said first clock pulses for simultaneously presenting a multiplicity of successively received digitized samples on respective outputs thereof; first and second memory means respectively storing first and second sets of interpolation coefficients which are functions of the carrier frequency, said first and second memory means having enabling inputs connected to said source for respectively receiving said second and third clock pulses therefrom;
Claim 3
Dependent Claim
172 words
a generator of address signals controlled by said first and second clock pulses, said generator being connected to said first and second memory means for reading out a multiplicity of first interpolation coefficients from said first memory means in the presence of a second clock pulse and for reading out a multiplicity of second interpolation coefficients from said second memory means in the presence of a third clock pulse; digital filter means with first and second inputs respectively connected to said first and second memory means and with other inputs connected to the outputs of said delay means for deriving from said digitized samples and from said first and second interpolation coefficients two interleaved trains of in-phase samples and quadrature samples; phase-correcting means connected to said digital filter means for recovering a phase-coherent baseband signal from said in-phase and quadrature samples; and synchronization-estimating means downstream of said phase-correcting means feeding back an error signal to said source for establishing an optimum relative time position of said first, second and third clock pulses.
Claim 4
Dependent Claim
172 words
a generator of address signals controlled by said first and second clock pulses, said generator being connected to said first and second memory means for reading out a multiplicity of first interpolation coefficients from said first memory means in the presence of a second clock pulse and for reading out a multiplicity of second interpolation coefficients from said second memory means in the presence of a third clock pulse; digital filter means with first and second inputs respectively connected to said first and second memory means and with other inputs connected to the outputs of said delay means for deriving from said digitized samples and from said first and second interpolation coefficients two interleaved trains of in-phase samples and quadrature samples; phase-correcting means connected to said digital filter means for recovering a phase-coherent baseband signal from said in-phase and quadrature samples; and synchronization-estimating means downstream of said phase-correcting means feeding back an error signal to said source for establishing an optimum relative time position of said first, second and third clock pulses.
Claim 5
Dependent Claim
118 words
A demodulator as defined in claim 1 wherein said source comprises an oscillator emitting a train of basic clock pulses at a cadence which is a multiple of the cadence of said first clock pulses and a different multiple of the cadence of said second and third clock pulses, frequency-dividing means connected to said oscillator for generating said first clock pulses, a programmed pulse counter connected to said oscillator in parallel with said frequency-dividing means for emitting a second clock pulse and resetting itself upon reaching a preset count modifiable by said error signal, and phase-shifting means connected to said programmed pulse counter for deriving said third clock pulses from the second clock pulses emitted by the latter.
Claim 6
Dependent Claim
70 words
A demodulator as defined in claim 2 wherein said generator comprises a further pulse counter connected to said oscillator for stepping by said basic clock pulses and to said frequency-dividing means for resetting by said first clock pulses, and gating means connected to said pulse counters for reading out the contents of said further pulse counter in the presence of a second clock pulse emitted by said programmed pulse counter.
Claim 7
Dependent Claim
171 words
A demodulator as defined in claim 1 wherein said digital filter means comprises a set of first memory cells connected to said first and second inputs, a set of second memory cells connected to said other inputs, first and second logic gates respectively inserted in said first and second inputs for loading said first memory cells with said first interpolation coefficients in the presence of said second clock pulses and with said second interpolation coefficients in the presence of said third clock pulses, further logic gates inserted in said other inputs for loading said second memory cells with said digitized samples in the presence of said second clock pulses, a set of digital multipliers connected to said first and second memory cells for producing the products of the interpolation coefficients and digitized samples respectively stored therein, and digital adding means for summing the products formed with said first interpolation coefficients to produce said in-phase samples and for summing the products formed with said second interpolation coefficients to produce said quadrature samples.
Claim 8
Dependent Claim
66 words
A demodulator as defined in claim 4 wherein said digital adding means is provided with a pair of parallel AND gates, one of said AND gates having an enabling input receiving said third clock pulses for passing said in-phase samples in their presence, the other of said AND gates having an enabling input receiving said second clock pulses for passing said quadrature samples in their presence.
References Cited (Backward Citations)
US4035735A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-16 | 1982-04-17 | 1982-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-16 | 1986-04-17 | 1986-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-16 | 1990-04-17 | 1990-10-17 | $7700.00 | Window Closed / Lapsed |