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Patent US4121057A successfully refreshed from Google Patents.
US4121057A
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Frame synchronizing device
Assignee: Alcatel CIT SA
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Filing: 1977-08-02
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Granted: 1978-10-17
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Expires: 1997-08-02
Abstract
Abstract The invention relates to the frame synchronization of a first binary pulse train with a second binary pulse train. According to the invention, three looped shift registers are provided which each have a capacity of one complete frame and two identical control circuits are provided which cyclically respectively connect the input and output of the device to the inputs and outputs of the registers. In the case of divergence of frequencies between the two pulse trains, one complete frame is either repeated twice or completely omitted.
Inventors
- 👤 Jacques Luder
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 13:31
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/02; H04J3/06; H04J3/062; H04J3/0626; H04L; H04L25/00; H04L25/02; H04L25/05
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
168 words
A device for synchronising a "frame" of a first data pulse train at a first bit rate to a second data pulse train at a second bit rate, the device comprising a memory, and first and second control circuits for activating respectively the loading of the memory in synchronism with "frame" pulses of the first pulse train, and the unloading of the memory in synchronism with "frame" pulses of the second pulse train; wherein the memory is constituted by three looped shift register units, each having a capacity of one complete frame, and wherein the two control circuits have identical structures and cyclically connect the input of the device to the inputs of the shift registers and likewise cyclically connect the outputs of the shift registers to the output of the device in such a way that each of the control circuits switches from one register unit to the next only if that next unit is not already activated at the switching instant by the other control circuit.
Claim 2
Independent Claim
168 words
A device for synchronising a "frame" of a first data pulse train at a first bit rate to a second data pulse train at a second bit rate, the device comprising a memory, and first and second control circuits for activating respectively the loading of the memory in synchronism with "frame" pulses of the first pulse train, and the unloading of the memory in synchronism with "frame" pulses of the second pulse train; wherein the memory is constituted by three looped shift register units, each having a capacity of one complete frame, and wherein the two control circuits have identical structures and cyclically connect the input of the device to the inputs of the shift registers and likewise cyclically connect the outputs of the shift registers to the output of the device in such a way that each of the control circuits switches from one register unit to the next only if that next unit is not already activated at the switching instant by the other control circuit.
Claim 3
Dependent Claim
93 words
A device according to claim 1, wherein the device includes two memories of three looped shift registers each, each memory processing one of the pulse trains and wherein the said first and second control circuits are so arranged that the first control circuit activates the loading of a first one of the memories and the unloading of the other memory and that the second circuit activates the complementary operations, one output signal from each control circuit serving both to switch the loading of one of the memories and the unloading of the other.
Claim 4
Dependent Claim
231 words
Apparatus for synchronizing at least one output of a first digital transmission system with the corresponding input of a second digital transmission system, said first and second digital transmission systems each providing a frame synchronizing signal and a bit synchronizing signal, which comprises: a first memory circuit comprising at least three looped shift register stages, each of said stages having a capacity which is at least equal to the length of one complete frame of the signal transmitted; a first control circuit, connected to the source of the frame synchronizing signal for said first digital transmission system, for loading the output signal from said first transmission system into said first memory circuit in synchronism with said first frame synchronizing signal; and a second control circuit, connected to the source of the frame synchronizing signal for said second digital transmission system, for unloading the signal stored in said first memory circuit in synchronism with said second frame synchronizing signal, said first and second control circuits cyclically connecting the output of said first transmission system to the inputs of said shift register stages and the outputs of said shift register stages to the corresponding input of said second transmission system such that each of said control circuits switches from one shift register to the other only if that unit is not already activated at the instant of switching by the other control circuit.
Claim 5
Dependent Claim
231 words
Apparatus for synchronizing at least one output of a first digital transmission system with the corresponding input of a second digital transmission system, said first and second digital transmission systems each providing a frame synchronizing signal and a bit synchronizing signal, which comprises: a first memory circuit comprising at least three looped shift register stages, each of said stages having a capacity which is at least equal to the length of one complete frame of the signal transmitted; a first control circuit, connected to the source of the frame synchronizing signal for said first digital transmission system, for loading the output signal from said first transmission system into said first memory circuit in synchronism with said first frame synchronizing signal; and a second control circuit, connected to the source of the frame synchronizing signal for said second digital transmission system, for unloading the signal stored in said first memory circuit in synchronism with said second frame synchronizing signal, said first and second control circuits cyclically connecting the output of said first transmission system to the inputs of said shift register stages and the outputs of said shift register stages to the corresponding input of said second transmission system such that each of said control circuits switches from one shift register to the other only if that unit is not already activated at the instant of switching by the other control circuit.
Claim 6
Dependent Claim
29 words
The apparatus according to claim 3 wherein each shift register stage includes: logic means for looping said shift register only when said shift register is activated for unloading thereof.
Claim 7
Dependent Claim
108 words
The apparatus according to claim 3 further comprising: a second memory circuit comprising at least three looped shift register stages, each of which has a capacity which is at least equal to the length of one complete frame of the signal transmitted, said first control circuit activating the loading of said first memory circuit and the unloading of said second memory circuit, and said second control circuit activating the loading of said second memory circuit and the unloading of said first memory circuit, one output signal from each control circuit serving both to switch the loading of one of the memory circuits and the unloading of the other.
Claim 8
Dependent Claim
108 words
The apparatus according to claim 4 further comprising: a second memory circuit comprising at least three looped shift register stages, each of which has a capacity which is at least equal to the length of one complete frame of the signal transmitted, said first control circuit activating the loading of said first memory circuit and the unloading of said second memory circuit, and said second control circuit activating the loading of said second memory circuit and the unloading of said first memory circuit, one output signal from each control circuit serving both to switch the loading of one of the memory circuits and the unloading of the other.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-10-16 | 1982-04-17 | 1982-10-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-10-16 | 1986-04-17 | 1986-10-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-10-16 | 1990-04-17 | 1990-10-17 | $7700.00 | Window Closed / Lapsed |