Quasi-static MOS memory array with standby operation

Claim 1

An MOS static memory array comprising, in combination, a plurality of MOS memory cells, means for writing information into said MOS memory cells, means for reading information contained in said MOS memory cells, and constant energy source means for maintaining the information state of said MOS memory cells during the period of time when there is no reading or writing operation being performed with said MOS memory cells, a plurality of Bit/Sense lines connected to said MOS memory cells, a plurality of Word line select decoder lines connected to said MOS memory cells, and a plurality of common return lines connected to said MOS memory cells, each of said common return lines having current sinking means for permitting current sinking into said current sinking means from all of said MOS memory cells connected to each of said common return lines during writing and reading operations, and means connected to each of said common return lines for permitting some current flow from each of said MOS memory cells connected to each of said common return lines to pass through said common return lines during the period of time when there is no reading or writing operation being performed with said MOS memory cells, said current sinking means comprising an MOS device, said current flow permitting means comprising only one resistor device, said resistor device being connected in parallel to said MOS device, each of said memory cells comprising four MOS devices, each of said four MOS devices having a gate electrode, a drain region and a source region, one of said four MOS devices having its gate electrode connected to one of said plurality of Word lines and its drain region connected to one of a pair of Bit/Sense lines, a second of said four MOS devices having its gate electrode connected to the same one of said plurality of Word line select decoder lines and its drain region connected to the second of said pair of Bit/Sense lines, a third and fourth of said four MOS devices connected up in a cross-coupled arrangement having the drain region of the third of said four MOS devices connected to the source region of said second of said four MOS devices and to the gate electrode of the fourth of said four MOS devices, the drain region of the fourth of said four MOS devices is connected to the source region of said one of said four MOS devices and to the gate electrode of the third of said four MOS devices, the source regions of both the third and fourth of said four MOS devices being connected to one of said plurality of common return lines that is associated with said one of said plurality of Word lines said memory array being adapted to operate at all times with a single power supply, said memory array being adapted to operate at all times with a +5 volt single power supply.