Patent US4117540A successfully refreshed from Google Patents.
US4117540A
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Computing module
Assignee: Commissariat à l'Énergie Atomique et Aux Énergies Alternatives
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Filing: 1977-01-13
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Granted: 1978-09-26
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Expires: 1997-01-13
Abstract
Abstract The computing module comprises a group of three circuits each intended to perform an elementary operation on the input signals and consisting of a summing circuit for receiving the signals E 1 and E 2 and delivering the sum signal S 1 = E 1 + E 2 , a subtracter for receiving the signals E 1 and E 2 and delivering the difference signal S 2 = E 1 - E 2 and a multiplier for receiving the signals E 1 and E 3 and delivering the product signal S 3 = E 1 E 3 , as well as a fourth circuit for performing a non-elementary operation on the input signals and delivering the signals S 4 .
Inventors
- 👤 Alain Bonnemay
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 16:04
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; H; H03; H03K; H03K19/00; H03K19/02; H03K19/173
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
123 words
A computing module having three inputs respectively e 1 , e 2 and e 3 , and four outputs, respectively s 1 , s 2 , s 3 and s 4 , wherein said module comprises: a summing circuit with two inputs respectively connected to e 1 and e 2 and one output connected to s 1 , a first subtracter with two inputs respectively connected to e 1 and e 2 and one output connected to s 2 , a multiplier with two inputs respectively connected to e 1 and e 3 and one output connected to s 3 , a second subtracter with two inputs respectively connected to s 1 and s 3 and one output connected to s 4 .
Claim 2
Dependent Claim
123 words
A computing module having three inputs respectively e 1 , e 2 and e 3 , and four outputs, respectively s 1 , s 2 , s 3 and s 4 , wherein said module comprises: a summing circuit with two inputs respectively connected to e 1 and e 2 and one output connected to s 1 , a first subtracter with two inputs respectively connected to e 1 and e 2 and one output connected to s 2 , a multiplier with two inputs respectively connected to e 1 and e 3 and one output connected to s 3 , a second subtracter with two inputs respectively connected to s 1 and s 3 and one output connected to s 4 .
Claim 3
Dependent Claim
122 words
A computing module having three inputs respectively e 1 , e 2 and e 3 , and four outputs, respectively s 1 , s 2 , s 3 and s 4 , wherein said module comprises: a summing circuit with two inputs respectively connected to e 1 and e 2 and one output connected to s 1 , a subtracter with two inputs respectively connected to e 1 and e 2 and one output connected to s 2 , a multiplier with two inputs respectively connected to e 1 and e 3 and one output connected to s 3 , a circuit with two inputs respectively connected to e 1 and e 2 and with one output connected to s 4 .
Claim 4
Dependent Claim
122 words
A computing module having three inputs respectively e 1 , e 2 and e 3 , and four outputs, respectively s 1 , s 2 , s 3 and s 4 , wherein said module comprises: a summing circuit with two inputs respectively connected to e 1 and e 2 and one output connected to s 1 , a subtracter with two inputs respectively connected to e 1 and e 2 and one output connected to s 2 , a multiplier with two inputs respectively connected to e 1 and e 3 and one output connected to s 3 , a circuit with two inputs respectively connected to e 1 and e 2 and with one output connected to s 4 .
Claim 5
Dependent Claim
14 words
A computing module according to claim 1, wherein two of the inputs are connected.
Claim 6
Dependent Claim
15 words
A computing module according to claim 1, wherein predetermined outputs are connected to predetermined inputs.
Claim 7
Dependent Claim
14 words
A computing module according to claim 2, wherein two of the inputs are connected.
Claim 8
Dependent Claim
15 words
A computing module according to claim 2, wherein predetermined outputs are connected to predetermined inputs.
Claim 9
Dependent Claim
16 words
A computing module according to claim 2, wherein said last mentioned circuit is a NAND gate.
Claim 10
Dependent Claim
16 words
A computing module according to claim 2, wherein said last mentioned circuit is a NOR gate.
Claim 11
Dependent Claim
16 words
A computing module according to claim 2, wherein said last mentioned circuit is a NOT gate.
Claim 12
Dependent Claim
16 words
A computing module according to claim 2, wherein said last-mentioned circuit is an exclusive -OR gate.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-09-25 | 1982-03-27 | 1982-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-09-25 | 1986-03-27 | 1986-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-09-25 | 1990-03-27 | 1990-09-26 | $7700.00 | Window Closed / Lapsed |