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US4117407A
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Frequency synthesizer tuner
Assignee: Toshiba Corp
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Filing: 1976-04-29
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Granted: 1978-09-26
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Expires: 1996-04-29
Abstract
Abstract The frequency synthesizer tuner is constituted by a dynamic shift register including first and second shift registers connected in a loop, wherein an information is written into and read out of the dynamic shift register and circulated therethrough by clock pulses, an output circuit including a display unit and a frequency synthesizer to which the information read out of the first shift register is supplied through a latch circuit, and a memory circuit connected in parallel with the latch circuit, a transfer circuit connected between the first and second shift registers, a refresh circuit connected between the output circuit and the second shift register, and a keyboard and a keyboard input circuit for applying an input information to the first shift register.
Inventors
- 👤 Hiromi Kusakabe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 12:31
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18; H03L7/183; H03J; H03J5/00; H03J5/02; H03J5/0245; H03J5/0272; H03J5/0281
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
160 words
A frequency synthesizer tuner comprising a dynamic shift register including first and second shift registers connected in a loop, wherein an information is written into and read out of said dynamic shift register and circulated therethrough by clock pulses, an output circuit including a display unit and a frequency synthesizer to which the information read out of said first shift register is supplied through a latch circuit, a memory circuit connected to the output of the latch circuit and having an output connected to the input of said latch circuit, a transfer circuit connected between said first and second shift registers for transferring the information from the first shift register into the second shift register for repeatedly supplying the information of said output circuit to said second shift register, a refresh circuit connected between said latch circuit and said second shift register, and a keyboard and a keyboard input circuit for applying an input information to said first shift register.
Claim 2
Dependent Claim
160 words
A frequency synthesizer tuner comprising a dynamic shift register including first and second shift registers connected in a loop, wherein an information is written into and read out of said dynamic shift register and circulated therethrough by clock pulses, an output circuit including a display unit and a frequency synthesizer to which the information read out of said first shift register is supplied through a latch circuit, a memory circuit connected to the output of the latch circuit and having an output connected to the input of said latch circuit, a transfer circuit connected between said first and second shift registers for transferring the information from the first shift register into the second shift register for repeatedly supplying the information of said output circuit to said second shift register, a refresh circuit connected between said latch circuit and said second shift register, and a keyboard and a keyboard input circuit for applying an input information to said first shift register.
Claim 3
Dependent Claim
25 words
A frequency synthesizer tuner according to claim 1, wherein said transfer circuit is connected between said first and second shift registers through said latch circuit.
Claim 4
Dependent Claim
22 words
A frequency synthesizer tuner according to claim 1, wherein said transfer circuit is directly connected between said first and second shift registers.
Claim 5
Dependent Claim
95 words
A frequency synthesizer tuner according to claim 1, wherein said second shift register consists of four bit shift register and an erroneous display preventing circuit is coupled to said second shift register, said erroneous display preventing circuit comprising means for obtaining the logical sum of fourth digit with third and second digits of the second shift register to detect BCD values corresponding to the decimal number 10 to 15, and means for obtaining the inversed logical data of the fourth digit to convert the obtained BCD data to the corresponding decimal numbers 2 to 7.
Claim 6
Dependent Claim
94 words
A frequency synthesizer tuner according to claim 1, wherein said keyboard is supplied with a plurality of digit select signals for driving AC-driven display elements and, from which a prescribed signal in said digit select signals is selectively delivered in response to the operated key in a plurality of keys, and said keyboard input circuit further comprises an input gate circuit the gate of which is opened with the timing of the same polarity as that of the digit select signal to transfer the output signal from said keyboard to a keyboard input unit.
Claim 7
Dependent Claim
115 words
A frequency synthesizer tuner according to claim 1, wherein said display unit includes a display unit driving circuit operating in an AC-driven mode or a DC-driven mode both of which are driven by a segment select signal and a digit select signal, said display unit driving circuit comprising a gate circuit adapted to include a bias frequency signal component into said segment select input signal and said digit select input signal in the AC-driven mode and to prevent the bias frequency signal component in the DC-driven mode to deliver directly said segment select input signal and digit select input signal, thereby providing a universal display unit driving circuit for both of AC-driven and DC-driven modes.
Claim 8
Dependent Claim
56 words
A frequency synthesizer tuner according to claim 1, wherein said display unit comprises a display unit driving circuit in which a predetermined number of digits is used to digitally display the received band frequency and the control wires of idle segments are used to display at least one of the received band and the frequency units.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-09-25 | 1982-03-27 | 1982-09-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-09-25 | 1986-03-27 | 1986-09-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-09-25 | 1990-03-27 | 1990-09-26 | $7700.00 | Window Closed / Lapsed |