Unbalanced sense circuit

Claim 1

A sense circuit for comparing the voltage produced by a first reference signal current having a first value with the voltage produced by a second signal current having either a first level approximately equal to said first value or a second level substantially different from said first level, comprising: first and second capacitive nodes; first and second inverters, each inverter having an input and an output; said first inverter having a different, predetermined, quiescent point than said second inverter for the same value of input bias applied to their respective input terminals; means connecting the input of said first inverter to said first node, and means connecting the input of said second inverter to said second node; a first biasing means connected between the input and the output of said first inverter for, during a first time interval, selectively providing a direct current connection therebetween and biasing said first inverter and said first node at a first quiescent point; a second biasing means connected between the input and the output of said second inverter for, during said first time interval, selectively providing a direct current connection therebetween and biasing said second inverter and said second node at a second quiescent point other than said first quiescent point whereby a predetermined voltage offset exists between the quiescent levels at said first and second nodes; means for, during a second time interval subsequent to said first time interval, supplying said first reference current to said first node; means for, during said second time interval, supplying said second signal current to said second node; the difference in the quiescent points of said first and second inverters being such that the resultant voltage offset between said first and second nodes is: (a) greater in amplitude than, and opposite in direction to, a given voltage difference generated, during said second time interval, between said first and second nodes when said second current is at said first level but exceeds said first current; and (b) substantially smaller in magnitude than the voltage differential generated, during said second time interval, between said first and second nodes when said first current has said first value and said second current has said second value; and selectively enabled cross-coupled means connected between the output of each one of said first and second inverters and the input of the other one of said first and second inverters for, during a third time interval subsequent to said second time interval, forming a flip-flop set to a first state when said first and second currents supplied to their respective nodes during said second time interval are of approximately equal value and set to its other stable state when said second signal current is at said second level and said first current has said first value.