Electrically alterable floating gate semiconductor memory device

Claim 2

An electrically programmable, non-volatile, floating gate, semiconductor memory array comprising: a plurality of MOS transistor devices each having a source, a drain, a floating gate, and a control gate, the transistor devices being arranged in an array of rows and columns; means for connecting the control gates of all devices in each row together to provide row lines; means connecting the sources of all devices in each column together to provide first column lines generally perpendicular to the row lines; means connecting the drains of all devices in each column together to provide second column lines generally parallel to the first column lines; means for selecting one of the row lines and applying a high voltage to it while applying a low voltage to the remaining row lines; means for selecting one of the first column lines and applying a low voltage to it while applying a high voltage to all of the other first column lines; means for applying high voltage to all of the second column lines; and means to deprogram the memory including means for applying low voltage to all of the second column lines.

Claim 3

A memory array according to claim 1 wherein the transistor devices are N-channel and the floating gate and control gate are polycrystalline silicon.

Claim 4

A memory array according to claim 2 wherein means are provided for reading data from the array by applying a voltage less than said high voltage to a selected one of the row lines and grounding a selected one of the first column lines.

Claim 5

A memory array according to claim 3 wherein an insulator between the floating gate and control gate in each of the transistor devices permits the floating gate to discharge when the source and drain are grounded and the control gate is at a high voltage.

Claim 6

A memory array according to claim 4 wherein the insulator between the floating gate and control gate is silicon oxide which is less than about 1200 A in thickness.

Claim 7

An electrically programmable, non-volatile, floating gate, semiconductor memory cell array comprising: a plurality of MOS transistors each having a source, a drain, floating gate, and a control gate; an insulating layer separating the floating gate and the control gate in each transistor; a gate insulator separating the floating gate from a channel region between the source and drain in each transistor; the MOS transistors being arranged in an array of rows and columns; row lines connecting together the control gates of all transistors in a row; first column lines generally normal to the row lines connecting together the sources of all transistors in a column; second column lines generally parallel to the first column lines connecting together the drains of all transistors in a column; means including a row line and a second column line for applying high voltage to the drain and control gate of a selected transistor while applying reference potential to the source to program the selected cell by charging the floating gate via electrons traversing the gate insulator; and means including the first and second column lines for applying reference potential to the sources and drains of the transistors while applying high voltage to the control gates to deprogram the cells by discharging the floating gates via current traversing the insulating layer.

Claim 8

An electrically programmable, non-volatile, floating gate, semiconductor memory cell array comprising: a plurality of MOS transistors each having a source, a drain, floating gate, and a control gate; an insulating layer separating the floating gate and the control gate in each transistor; a gate insulator separating the floating gate from a channel region between the source and drain in each transistor; the MOS transistors being arranged in an array of rows and columns; row lines connecting together the control gates of all transistors in a row; first column lines generally normal to the row lines connecting together the sources of all transistors in a column; second column lines generally parallel to the first column lines connecting together the drains of all transistors in a column; means including a row line and a second column line for applying high voltage to the drain and control gate of a selected transistor while applying reference potential to the source to program the selected cell by charging the floating gate via electrons traversing the gate insulator; and means including the first and second column lines for applying reference potential to the sources and drains of the transistors while applying high voltage to the control gates to deprogram the cells by discharging the floating gates via current traversing the insulating layer.

Claim 9

A memory cell array according to claim 6 wherein the insulating layer is silicon oxide having a thickness less than about 1200 A.

Claim 10

A memory cell array according to claim 6 wherein the MOS transistor is N-channel and the floating gate and control gate are polycrystalline silicon.

Claim 11

A memory cell array according to claim 8 wherein the insulating layer is thermally-grown silicon dioxide.

Claim 12

A memory cell array according to claim 9 wherein the insulating layer is not more than 150% as thick as the gate insulator.