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US4112487A Expired / Lapsed US ⏱️ 0.0 years remaining

Apparatus for writing data in unique order into and retrieving same from memory

Assignee: Ferranti International PLC
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Filing: 1976-11-16
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Granted: 1978-09-05
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Expires: 1996-11-16
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Abstract

Abstract Data processing apparatus includes a storage circuit or memory, and an addressing circuit for identifying word locations within the storage circuit into and from which a plurality of information items are to be written and read, respectively. Further, there is included an encoding circuit for encoding at least a part of each information item in one-out-of-n code, illustratively. In turn, the encoded part is successively shifted by a shift circuit so that it is stored in the storage circuit in a manner that the stored information in each word location has a bit order different from that order of any other information item as stored in the storage circuit. A translating or de-skewing circuit is provided for shifting the encoded data items as read out from the storage circuit in a direction opposite to that imparted by the first noted shift circuit.

Inventors

  • 👤 Geoffrey Nutter
  • 👤 William McGibbon

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 15:57
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0207

Claims Analysis

Total Claims: 2
Claim 1
Independent Claim 289 words
Data processing appartus for processing a plurality of information items, said data processing apparatus comprising: a. a memory having an input and an output, and operable in a write mode for receiving and storing at least a portion of each of the plurality of information items into a plurality of corresponding multi-bit word locations and in a read mode, for reading out information items from said plurality of word location; b. an addressing circuit for addressing selected word locations of said memory in both the write and read modes of operation; c. loading means coupled to said input of said memory and including an encoder circuit for receiving and encoding said portion of each said plurality of information items, and a shift circuit for successively imparting to said encoded portion of each of said plurality of information items a shift of a predetermined number of bits in a predetermined direction, whereby said encoded portion of each of said plurality of information items is stored into a separate multi-bit word location as determined by said address circuit in a manner that one of said stored information items has a sequence of bits arranged in order different from that order of any other stored information item; d. translating means coupled to said output of said memory for reading out simultaneously from said memory a single bit of each of said plurality of information items stored in said plurality of corresponding word locations and applying a shift of said predetermined number of bits to said single bits in a direction reversed to said predetermined direction; and e. comparator means coupled to said output of said memory for comparing one of said single bits with another selected bit from a different information item.
Claim 2
Dependent Claim 289 words
Data processing appartus for processing a plurality of information items, said data processing apparatus comprising: a. a memory having an input and an output, and operable in a write mode for receiving and storing at least a portion of each of the plurality of information items into a plurality of corresponding multi-bit word locations and in a read mode, for reading out information items from said plurality of word location; b. an addressing circuit for addressing selected word locations of said memory in both the write and read modes of operation; c. loading means coupled to said input of said memory and including an encoder circuit for receiving and encoding said portion of each said plurality of information items, and a shift circuit for successively imparting to said encoded portion of each of said plurality of information items a shift of a predetermined number of bits in a predetermined direction, whereby said encoded portion of each of said plurality of information items is stored into a separate multi-bit word location as determined by said address circuit in a manner that one of said stored information items has a sequence of bits arranged in order different from that order of any other stored information item; d. translating means coupled to said output of said memory for reading out simultaneously from said memory a single bit of each of said plurality of information items stored in said plurality of corresponding word locations and applying a shift of said predetermined number of bits to said single bits in a direction reversed to said predetermined direction; and e. comparator means coupled to said output of said memory for comparing one of said single bits with another selected bit from a different information item.

References Cited (Backward Citations)

US3270324A Cited
US3535694A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1981-09-04 1982-03-06 1982-09-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1985-09-04 1986-03-06 1986-09-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1989-09-04 1990-03-06 1990-09-05 $7700.00 Window Closed / Lapsed

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