US4110713A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low offset field effect transistor correlator circuit
Assignee: United States Department of the Air Force
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Filing: 1976-11-19
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Granted: 1978-08-29
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Expires: 1996-11-19
Abstract
Abstract A low offset field effect transistor correlator circuit where one signal is applied to a balanced input through capacitors to the drain and source electrodes of a field effect transistor and having a second signal applied to the gate of the transistor. Low pass filters are connected to the source and drain, and the correlated input signals appear across resistors connecting the outputs of the filters.
Inventors
- 👤 Gayle P. Martin
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:47
CPC Classifications
G; G06; G06G; G06G7/00; G06G7/12; G06G7/19; G06G7/1928
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
114 words
A low offset field effect transistor correlator circuit for adaptive processors comprising: a field effect transistor means so constructed as to include interchangeable source and drain terminals and gate means for controlling the resistivity in the transistor means; a first signal input means connected to the source and drain terminals; capacitor means connected between the first signal means and the source and drain terminal means; a second signal input means connected to the said transistor gate means; signal output means; low pass filter means connecting the said transistor source and drain terminals and the signal output means, and load resistor means connected between the output from the source and output from the drain terminals.
Claim 2
Dependent Claim
114 words
A low offset field effect transistor correlator circuit for adaptive processors comprising: a field effect transistor means so constructed as to include interchangeable source and drain terminals and gate means for controlling the resistivity in the transistor means; a first signal input means connected to the source and drain terminals; capacitor means connected between the first signal means and the source and drain terminal means; a second signal input means connected to the said transistor gate means; signal output means; low pass filter means connecting the said transistor source and drain terminals and the signal output means, and load resistor means connected between the output from the source and output from the drain terminals.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-08-28 | 1982-02-27 | 1982-08-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-08-28 | 1986-02-27 | 1986-08-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-08-28 | 1990-02-27 | 1990-08-29 | $7700.00 | Window Closed / Lapsed |