Cipher computer and cryptographic system

Claim 2

In a system for the implementation of a cipher computer and cryptographic system, the combination of: a first memory means for storing a first signal S, said first memory means having storage locations for n words S n ; a second memory means for storing a second signal K, said second memory means having storage locations for n words K n ; crypto means having as input the stored outputs S n , K n of said first and second memory means and providing at its output the cipher product of said first and second signals, with said stored outputs S n , K n representing at least one of delayed, encrypted, and decrypted signals S, K and with said cipher product representing the cipher function f(S, K) =S n K n where the subscript n indicates that n delay operations by said first and second memory means and n encrypting operations including at least one of multiplying, permuting and substituting by said crypto means have been performed on said first signal S using said second signal K to obtain the output cipher function f(S, K) as one of stream and block ciphers, said crypto means including one of a multiplier and algorithm computer, where said multiplier encrypts a stream cipher function f(S, K) and said algorithm computer encrypts a block cipher function f(S, K); and recirculation means providing a feedback path from one of the output of said first and second memory means and said crypto means to the input of one of said first and second memory means and including DELTIC feedback means in the form of a delay register.

Claim 3

The system of claim 1 wherein said first and second memory and crypto means are analog menas.

Claim 4

The system of claim 1 wherein said first and second memory and crypto means are digital means.

Claim 5

The system of claim 1 including: an address counter connected to said first and second memory means for addressing n storage locations of said memory means in a sampling interval providing n outputs; and clock means connected to said first and second memory means and to said address counter, including means for shifting signals in at least said first memory means after each sampling interval.

Claim 6

The system of claim 4 wherein said clock means includes means for shifting signals in said second memory means after each sampling interval.

Claim 7

The system of claim 1 wherein said crypto means computes the encryption algorithm gives in the Federal Register Mar. 17, 1975.

Claim 8

The system of claim 1 wherein said crypto means computes the encryption algorithm of Vernam's cipher.

Claim 9

The system of claim 1 wherein said memory means are RAMs.

Claim 12

The method of claim 9 including analog storing of signals.

Claim 13

The method of claim 9 including digital storing of signals.

Claim 14

The method of claim 9 including the steps of: accessing said memory means with an address counter; and timing the operation of said memory means with a clock.

Claim 15

The method of claim 9 including the step of shifting signals in at least one of said memory means after each sampling interval.

Claim 16

The method of claim 9 including the step of computing the encryption algorithm given in the Federal Register Mar. 17, 1975.

Claim 17

The method of claim 9 including the step of computing the encryption algorithm of Vernam's cipher.

Claim 18

The method of claim 9 including the step of storing the signals in a RAM.

Claim 19

In a system for the inmplementation of a cipher computer and cryptographic system, the combination of: a first memory means for storing a first signal S, said first memory means having storage locations for n words S n ; a second memory means for storing a second signal K, said second memory means having storage locations for n words K n ; crypto means having as input the stored outputs S n , K n of said first and second memory means and providing at its output the cipher product of said first and second signals, with said stored outputs S n , K n representing at least one of delayed, encrypted, and decrypted signals S, K, and with said cipher product representing the cipher function f(S, K)=S n K n where the subscript n indicates that n delay operations by said first and second memory means and n encrypting operations including at least one of multiplying, permuting and substituting by said crypto means have been performed on said first signal S using said second signal K to obtain the output cipher function f(S, K) as one of stream and block ciphers, said crypto means including one of a multiplier and algorithm computer, where said multiplier encrypts a stream cipher function f(S, K) and said algorithm computer encrypts a block cipher function f(S, K); and recirculation means providing a feedback path from one of the output of said first and second memory means and said crypto means to the input of one of said first and second memory means and including DELTIC feedback means in the form of an algorithm computer.

Claim 20

In a system for the inmplementation of a cipher computer and cryptographic system, the combination of: a first memory means for storing a first signal S, said first memory means having storage locations for n words S n ; a second memory means for storing a second signal K, said second memory means having storage locations for n words K n ; crypto means having as input the stored outputs S n , K n of said first and second memory means and providing at its output the cipher product of said first and second signals, with said stored outputs S n , K n representing at least one of delayed, encrypted, and decrypted signals S, K, and with said cipher product representing the cipher function f(S, K)=S n K n where the subscript n indicates that n delay operations by said first and second memory means and n encrypting operations including at least one of multiplying, permuting and substituting by said crypto means have been performed on said first signal S using said second signal K to obtain the output cipher function f(S, K) as one of stream and block ciphers, said crypto means including one of a multiplier and algorithm computer, where said multiplier encrypts a stream cipher function f(S, K) and said algorithm computer encrypts a block cipher function f(S, K); and recirculation means providing a feedback path from one of the output of said first and second memory means and said crypto means to the input of one of said first and second memory means and including DELTIC feedback means in the form of an algorithm computer.

Claim 21

The system of claim 17 wherein said first and second memory and crypto means are analog means.

Claim 22

The system of claim 17 wherein said first and second memory and crypto means are digital means.

Claim 23

The system of claim 17 including: an address counter connected to said first and second memory means for addressing n storage locations of said memory means in a sampling interval providing n outputs; and clock means connected to said first and second memory means and to said address counter, including means for shifting signals in at least said first memory means after each sampling interval.

Claim 24

The system of claim 20 wherein said clock means includes means for shifting signals in said second memory means after each sampling interval.

Claim 25

The system of claim 17 wherein said crypto means computes the encryption algorithm given in the Federal Register Mar. 17, 1975.

Claim 26

The system of claim 17 wherein said crypto means computes the encryption algorithm of Vernam's cipher.

Claim 27

The system of claim 17 wherein said memory means are RAMs.

Claim 30

The method of claim 25 including analog storing of signals.

Claim 31

The method of claim 25 including digital storing of signals.

Claim 32

The method of claim 25 including the steps of: accessing said memory means with an address counter; and timing the operation of said memory means with a clock.

Claim 33

The method of claim 28 including the step of shifting signals in at least one of said memory means after each sampling interval.

Claim 34

The method of claim 25 including the step of computing the encryption algorithm given in the Federal Register Mar. 17, 1975.

Claim 35

The method of claim 25 including the step of computing the encryption algorithm of Vernam's cipher.

Claim 36

The method of claim 25 including the step of storing the signals in a RAM.