Circuit and method for digitally measuring signal levels of pcm encoded signals

Claim 2

A digital circuit for measuring the level of a PCM signal representing an analogue signal and encoded in accordance with a predetermined companding law, comprising: a selector means having positions 0-n; a sampling circuit for successively sampling said PCM signal 2 n times, n being determined by said selector means; means for converting each of said samples to its normalized power representation; means for computing the average power of said samples; and means for determining the power level number of said average power.

Claim 3

A digital circuit as defined in claim 1 wherein said converting means is a first memory means wherein each location contains the square of the linear representation of its respective address, each of the addresses corresponding to a possible one of said coded samples.

Claim 4

A digital circuit as defined in claim 2 wherein said computing means comprises: an accumulator circuit responsive to the output signals from said first memory means and to clock signals from a control circuit for producing first and second output signals, said first output signal being a parallel data word consisting of the eight most significant bits of the accumulated sum of the normalized power of said samples, and said second output signal being a data word representing the position of the most significant one of said accumulated sum; a second memory means having a plurality of storage locations each containing the log 2 value of its respective address, each of the addresses corresponding to a possible one of said first signals; means for addressing said second memory means at the address defined by said first signal; and circuit means for producing a third output signal representing the exponent value of the average normalized power of said samples.

Claim 5

A digital circuit as defined in claim 3 wherein the circuit means comprises, a counter circuit responsive to said second signal for producing said third output signal corresponding to the exponent value thereof on the basis of the value of the most significant bit of said second output signal and said counter means also being responsive to a signal from said selector means for subtracting the value of n from said third signal, whereby said third signal represents the average normalized power of said samples.

Claim 6

A digital circuit as defined in claim 3 wherein said accumulator circuit comprises: a counter circuit responsive to the exponent portion of the output signal from the first memory means for providing an enable signal after a predetermined count as determined by said exponent portion; a parallel to serial shift register adapted to be loaded with the mantissa portion of the output signal from the first memory means, and responsive to said enable signal for providing a serial output signal of its contents; a shift register and an adder circuit for determining the accumulated sum of said mantissa portions of said n samples.

Claim 7

A digital circuit as defined in claim 4 wherein the means for determining the power level number of said average power is a pair of multiplication circuits, one for providing the product of said third output signal and a conversion constant, and the other for providing the product of the output signal from the second memory means and said conversion constant.

Claim 8

A digital circuit as defined in claim 6 and further comprising a converter circuit for combining and converting the output signals from the multiplication circuits into the binary coded decimal equivalent and a visual display means for viewing the output signal thereof.