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US4097986A
Expired / Lapsed
US
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Manufacturing process for the collective production of semiconductive junction devices
Assignee: Thales SA
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Filing: 1976-12-09
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Granted: 1978-07-04
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Expires: 1996-12-09
Abstract
Abstract A process intended for combining the "flip-chip bonding" technique with a method yielding diodes of very thin substrate forming mesa units or clumps etched out in a dielectric block embedding the semiconductor body. The process comprises, starting from a semiconductive wafer, a double mesa etching and a double lapping, each of them carried out on each side of the wafer, due to a thick dielectric layer and a thick metallic support respectively brought in at the right moment.
Inventors
- 👤 Raymond Henry
- 👤 Alain Chapard
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 19:52
CPC Classifications
H; H10; H10D; H10D8/00; H10D8/01; H10W; H10W70/00; H10W70/01; H10W70/02
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
178 words
A manufacturing process for the collective production of semiconductor devices, comprising the following steps: A. starting from a semiconductor wafer of a predetermined type of conductivity, forming a first layer of said type of conductivity more weakly doped than said wafer, then forming at least a second semiconductive layer of the opposite type of conductivity; B. creating grooves by mesa etching of the wafer on the side of said layers; C. filling said grooves with a dielectric material and lapping said wafer on the side of said material to make it level with said layers; D. depositing a conductive layer onto the flat surface formed at step (C); E. adding metal to form a heat-dissipating support; F. lapping said wafer on its free face so as to bring it to a uniform thickness less than the depth of said grooves; G. selectively depositing metal onto the surface obtained at step (F) to cover the semiconductive material left by said lapping; H. etching said dielectric material to obtain grooves onto said wafer; I. cutting said wafer along said grooves.
Claim 2
Dependent Claim
178 words
A manufacturing process for the collective production of semiconductor devices, comprising the following steps: A. starting from a semiconductor wafer of a predetermined type of conductivity, forming a first layer of said type of conductivity more weakly doped than said wafer, then forming at least a second semiconductive layer of the opposite type of conductivity; B. creating grooves by mesa etching of the wafer on the side of said layers; C. filling said grooves with a dielectric material and lapping said wafer on the side of said material to make it level with said layers; D. depositing a conductive layer onto the flat surface formed at step (C); E. adding metal to form a heat-dissipating support; F. lapping said wafer on its free face so as to bring it to a uniform thickness less than the depth of said grooves; G. selectively depositing metal onto the surface obtained at step (F) to cover the semiconductive material left by said lapping; H. etching said dielectric material to obtain grooves onto said wafer; I. cutting said wafer along said grooves.
Claim 3
Dependent Claim
22 words
A manufacturing process as claimed in claim 1, wherein, at step (C), said filling is obtained by the deposition of molten glass.
Claim 4
Dependent Claim
37 words
A manufacturing process as claimed in claim 1, wherein at step (G) said selective deposit combines at least two diodes and at step (H) etching takes place along a line surrounding the diodes joined by said deposit.
Claim 5
Dependent Claim
20 words
A manufacturing process as claimed in claim 1, wherein at step (G) said selective deposit only covers said semiconductor material.
Claim 6
Dependent Claim
25 words
A manufacturing process as claimed in claim 1, wherein at step (G) said selective deposit simultaneously covers said semiconductor material and dielectric material surrounding it.
Claim 7
Dependent Claim
27 words
A manufacturing process as claimed in claim 1, wherein at step (H) etching of said dielectric material is continued up to the layer deposited at step (D).
Claim 8
Dependent Claim
26 words
A manufacturing process as claimed in claim 6, wherein at the step (H) etching of said dielectric material is continued to the point of complete removal.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-07-03 | 1982-01-02 | 1982-07-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-07-03 | 1986-01-02 | 1986-07-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-07-03 | 1990-01-02 | 1990-07-04 | $7700.00 | Window Closed / Lapsed |