US4096560A — Protection circuit to minimize the effects of pow…

Claim 1

Independent Claim 193 words

In a system including an electronic memory and a microprocessor to control the reading or writing of data into said memory, a protection circuit to prevent the loss or alteration of memory data as a result of power line interruptions, said protection circuit comprising: power level detecting means having input and output terminal means, said level detecting means sampling the line power at said input terminal means thereof, first and second multivibrator devices connected to said output terminal means of said level detecting means, said first multivibrator device responsive to increasing power levels and said second multivibrator device responsive to decreasing power levels, and microprocessor and memory control gates connected to said first and second multivibrator devices in order to receive output signals therefrom that are indicative of either an out of tolerance power line interruption or in tolerance power line stabilization, said microprocessor and memory control gates adapted to selectively apply respective control signals to said microprocessor and to said memory to, thereby, inhibit the reading or writing of data into said memory and to maintain said microprocessor in a reset mode of operation during the occurrence of undesirable power line interruptions.

Claim 2

Dependent Claim 193 words

In a system including an electronic memory and a microprocessor to control the reading or writing of data into said memory, a protection circuit to prevent the loss or alteration of memory data as a result of power line interruptions, said protection circuit comprising: power level detecting means having input and output terminal means, said level detecting means sampling the line power at said input terminal means thereof, first and second multivibrator devices connected to said output terminal means of said level detecting means, said first multivibrator device responsive to increasing power levels and said second multivibrator device responsive to decreasing power levels, and microprocessor and memory control gates connected to said first and second multivibrator devices in order to receive output signals therefrom that are indicative of either an out of tolerance power line interruption or in tolerance power line stabilization, said microprocessor and memory control gates adapted to selectively apply respective control signals to said microprocessor and to said memory to, thereby, inhibit the reading or writing of data into said memory and to maintain said microprocessor in a reset mode of operation during the occurrence of undesirable power line interruptions.

Claim 3

Dependent Claim 170 words

A protection circuit to disable each of an electronic memory and an associated microprocessor control circuit during an interval of input line disturbances, said protection circuit including: power line detection means connected to an input power line to sense input line disturbances, first and second monostable means connected to output terminal means of said power level detection means to receive signals therefrom, said first monostable means responsive to input power coming up line disturbances and said second monostable means responsive to input power going down line disturbances, and control gating means respectively connected between said first and second monostable means and said electronic memory and microprocessor control circuit, said control gating means receiving signals from said first and second monostable means that are indicative of either a power coming up or power going down disturbance, whereby said control gating means applies control signals to inhibit the reading and writing of said memory and to delay the operation of said microprocessor control circuit during the occurrence of the power line disturbances.

Claim 4

Dependent Claim 170 words

A protection circuit to disable each of an electronic memory and an associated microprocessor control circuit during an interval of input line disturbances, said protection circuit including: power line detection means connected to an input power line to sense input line disturbances, first and second monostable means connected to output terminal means of said power level detection means to receive signals therefrom, said first monostable means responsive to input power coming up line disturbances and said second monostable means responsive to input power going down line disturbances, and control gating means respectively connected between said first and second monostable means and said electronic memory and microprocessor control circuit, said control gating means receiving signals from said first and second monostable means that are indicative of either a power coming up or power going down disturbance, whereby said control gating means applies control signals to inhibit the reading and writing of said memory and to delay the operation of said microprocessor control circuit during the occurrence of the power line disturbances.

Claim 5

Dependent Claim 20 words

The protection circuit recited in claim 2, wherein each of said first and second monostable means comprises a one-shot multivibrator.

Claim 6

Dependent Claim 19 words

The protection circuit recited in claim 3, wherein each of said one-shot multivibrators is a retriggerable, battery powered device.

Claim 7

Dependent Claim 80 words

The protection circuit recited in claim 2, wherein said control gating means comprises first and second logic gates, said first logic gate having input terminal means connected to respective first output terminals of each of said first and second monostable means and output terminal means connected to said electronic memory, and said second logic gate having input terminal means connected to a second output terminal of said first monostable means and output terminal means connected to said microprocessor control circuit.

Claim 8

Dependent Claim 79 words

The protection circuit recited in claim 5, wherein said first logic gate receives input signals having a first polarity from the first output terminals of said first and second monostable means to inhibit the reading or writing of said electronic memory, and said second logic gate receives input signals having a second polarity from the second output terminal of said second monostable means to delay the operation of said microprocessor control circuit during the occurrences of power line disturbances.

Claim 9

Dependent Claim 65 words

The protection circuit recited in claim 2, wherein said power level detection means comprises a multi-terminal semiconductor device, a first conduction path terminal thereof connected to said input power line, a second conduction path terminal thereof connected to said level detection output terminal means, and a control terminal thereof connected to one electrode of a diode means to regulate the conductivity of said semiconductor device.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1981-06-19	1981-12-19	1982-06-20	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1985-06-19	1985-12-19	1986-06-20	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1989-06-19	1989-12-19	1990-06-20	$7700.00	Window Closed / Lapsed

Protection circuit to minimize the effects of power line interruptions on the contents of a volatile electronic memory

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