US4095282A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory including varactor circuit to boost address signals
Assignee: Westinghouse Electric Corp
•
Filing: 1976-11-23
•
Granted: 1978-06-13
•
Expires: 1996-11-23
Abstract
Abstract A nonvolatile (MNOS) memory array using varactor boosted select signals is disclosed. The memory utilizes a varactor circuit to boost the row select during the erase and write modes of operation.
Inventors
- 👤 Harry G. Oehler
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 03:17
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/10; G11C16/04; G11C16/0466; H; H10; H10D; H10D30/00; H10D30/60; H10D30/69
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
81 words
An MNOS memory array comprising: a. an array of MNOS memory transistors, said array being arranged in columns and rows; b. first addressing means responsive to a first digital signal to generate a column select signal; c. second addressing means responsive to a second digital signal to generate a row select signal; and d. varactor means responsive to said row select signal and a write mode signal to boost said row select signal when said memory is in the write mode.
Claim 2
Dependent Claim
81 words
An MNOS memory array comprising: a. an array of MNOS memory transistors, said array being arranged in columns and rows; b. first addressing means responsive to a first digital signal to generate a column select signal; c. second addressing means responsive to a second digital signal to generate a row select signal; and d. varactor means responsive to said row select signal and a write mode signal to boost said row select signal when said memory is in the write mode.
Claim 3
Dependent Claim
81 words
An MNOS memory array comprising: a. an array of MNOS memory transistors, said array being arranged in columns and rows; b. first addressing means responsive to a first digital signal to generate a column select signal; c. second addressing means responsive to a second digital signal to generate a row select signal; and d. varactor means responsive to said row select signal and an erase mode signal to boost said row select signal when said memory is in the erase mode.
Claim 4
Dependent Claim
81 words
An MNOS memory array comprising: a. an array of MNOS memory transistors, said array being arranged in columns and rows; b. first addressing means responsive to a first digital signal to generate a column select signal; c. second addressing means responsive to a second digital signal to generate a row select signal; and d. varactor means responsive to said row select signal and an erase mode signal to boost said row select signal when said memory is in the erase mode.
Claim 5
Dependent Claim
130 words
An MNOS memory system comprising: a. an array of MNOS memory transistor arranged in rows and columns; b. first addressing means responsive to a first digital number to generate a column select signal; c. second addressing means responsive to a second digital number to generate a select signal; d. source follower circuit means for coupling said select signal to said array and to a varactor boost circuit to store charges in said varactor; and e. means for coupling a mode signal to said varactor to generate a row select signal at the output of said source follower circuit means, said row select signal having an amplitude and polarity sufficient to turn off the output stage of said source follower means thereby isolating said select signal from said source follower means.
Claim 6
Dependent Claim
130 words
An MNOS memory system comprising: a. an array of MNOS memory transistor arranged in rows and columns; b. first addressing means responsive to a first digital number to generate a column select signal; c. second addressing means responsive to a second digital number to generate a select signal; d. source follower circuit means for coupling said select signal to said array and to a varactor boost circuit to store charges in said varactor; and e. means for coupling a mode signal to said varactor to generate a row select signal at the output of said source follower circuit means, said row select signal having an amplitude and polarity sufficient to turn off the output stage of said source follower means thereby isolating said select signal from said source follower means.
References Cited (Backward Citations)
US4027294A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-06-12 | 1981-12-12 | 1982-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-06-12 | 1985-12-12 | 1986-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-06-12 | 1989-12-12 | 1990-06-13 | $7700.00 | Window Closed / Lapsed |