US4095145A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Display of variable length vectors
Assignee: United States Department of the Army
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Filing: 1976-12-13
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Granted: 1978-06-13
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Expires: 1996-12-13
Abstract
Abstract A variable length vector display system allows visual indication of the sd and direction of aircraft or moving vehicles, maintaining a constant illumination on the face of a cathode ray tube independent of the vector length or vector movement. The vector length from the target vehicle coordinate points to the predicted intercept coordinate points are displayed. Voltages defining the origin and the end point of a vector to be displayed are coupled through respective comparator and arithmetic units, scaled to provide a deflection factor, multiplied, and coupled through respective controlled integrator circuits. The integrators are controlled by a variable gate which operates as a function of the input signal, thereby varying the on-off time of the integrators for simultaneous operation. Output signals from the integrator circuits are coupled to respective X and Y deflection circuits of a cathode ray tube load. In conjunction with the input zero reference or origin signal the signals are combined to provide the appropriate X and Y deflection potential for the tube.
Inventors
- 👤 A. P. Terranova
- 👤 F. J. Murphy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 19:34
CPC Classifications
G; G01; G01R; G01R13/00; G01R13/20; G01R13/208
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
211 words
A variable length vector display circuit comprising: a cathode ray tube having X deflection means and Y deflection means; first and second comparators each having first and second inputs disposed to receive input voltage signals and an output; first and second operational amplifier sweep generators each having an input, an output, and a control input; the input of said first sweep generator being coupled to the output of said first comparator and the input of said second sweep generator being coupled to the output of said second comparator, the output of said first sweep generator being coupled to the X deflection means of said cathode ray tube and the output of said second sweep generator being coupled to the Y deflection means of said cathode ray tube; an arithmetic unit having first and second inputs and an output, said first input being connected to the output of said first comparator and said second input being connected to the output of said second comparator; a variable gate generator having an input coupled to the output of said arithmetic unit and an output coupled to the respective control inputs of said sweep generators for gating said sweep generators to controllably vary the sweep output voltage of said generators coupled to said deflection means.
Claim 2
Dependent Claim
211 words
A variable length vector display circuit comprising: a cathode ray tube having X deflection means and Y deflection means; first and second comparators each having first and second inputs disposed to receive input voltage signals and an output; first and second operational amplifier sweep generators each having an input, an output, and a control input; the input of said first sweep generator being coupled to the output of said first comparator and the input of said second sweep generator being coupled to the output of said second comparator, the output of said first sweep generator being coupled to the X deflection means of said cathode ray tube and the output of said second sweep generator being coupled to the Y deflection means of said cathode ray tube; an arithmetic unit having first and second inputs and an output, said first input being connected to the output of said first comparator and said second input being connected to the output of said second comparator; a variable gate generator having an input coupled to the output of said arithmetic unit and an output coupled to the respective control inputs of said sweep generators for gating said sweep generators to controllably vary the sweep output voltage of said generators coupled to said deflection means.
Claim 3
Dependent Claim
53 words
A variable length vector display circuit as set forth in claim 1 wherein said first input of said first comparator is coupled to provide a second input signal to said X deflection means and said first input of said second comparator is coupled to provide a second input to said Y deflection means.
Claim 4
Dependent Claim
107 words
A variable length vector display circuit as set forth in claim 2 and further comprising an inverter having an input and an output, said input being coupled to the output of said arithmetic unit; first and second multiplier circuits having first and second inputs and an output, the output of said inverter being coupled as said first inputs of said first and second multipliers, the outputs of said first and second comparators being coupled to the second inputs respectively of said first and second multipliers, and the outputs of said first and second multipliers being coupled to the inputs of said first and second sweep generators respectively.
Claim 5
Dependent Claim
55 words
A variable length vector display circuit as set forth in claim 3 wherein said sweep generators are integrating circuits and further comprising first and second amplifiers coupled between the output of said first and second comparators respectively and the second inputs of said first and second multipliers respectively for scaling the voltage signals coupled therebetween.
Claim 6
Dependent Claim
48 words
A variable length vector display circuit as set forth in claim 4 and further comprising a unijunction transistor coupled across each of said integrator circuits, said unijunction switches being emitter coupled to the control input coupled to said variable gate generator for simultaneously activating and de-activating said integrators.
Claim 7
Dependent Claim
82 words
A variable length vector display circuit as set forth in claim 5 and further comprising first and second summing amplifiers coupled respectively between the outputs of said integrating circuits and the inputs to said deflection means, each of said summing amplifiers having a first input coupled to receive said respective integrating circuit outputs, an output coupled to respective deflection circuits, and a second input coupled to receive respective of said second input signals to said deflection means coupled from said comparator inputs.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-06-12 | 1981-12-12 | 1982-06-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-06-12 | 1985-12-12 | 1986-06-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-06-12 | 1989-12-12 | 1990-06-13 | $7700.00 | Window Closed / Lapsed |