Abstract This disclosure relates to a demultiplexer for a pair of digital groups (digroups) which are synchronously multiplexed into a composite signal by bit interleaving the pair. The composite multiplex signal is coupled to each of a pair of gating circuits. A clock recovery circuit recovers the timing of the composite signal and generates therefrom a pair of phase inverted clock signals. These clock signals are respectively coupled to the two gating circuits to alternately enable the same and thereby steer the interleaved digroup bits to separate digroup receive units. A comparison circuit is coupled to each receive unit to compare the relative timing of the bits delivered thereto; this comparison utilizes the fact that multiplexing is done with the bits of one digroup preceding the bits of the other. If the steering is incorrect and the respective digroup bit streams are being sent to the wrong receive units, the comparison circuit generates a signal which serves to phase reverse the clock signals and consequently the enabling of the gating circuits. This reverses, and thereby corrects, the steering of the digroup bit streams.
In a communication system wherein a pair of n-channel digroup signals, each of which includes framing bits, are synchronously multiplexed into a composite signal by bit interleaving the digroup signals, a demultiplexer comprising a pair of gating means to which the composite signal is coupled, means for recovering the timing of said composite signal and for generating therefrom a pair of phase inverted clock signals each at the digroup bit rate, means for respectively coupling said clock signals to said gating means to alternately enable the same and thereby steer the interleaved digroup bits of said composite signal to separate digroup receive units, means for comparing the relative timing of the bits coupled to each of the receive units and for generating a predetermined signal when the digroup bit streams are being sent to the wrong receive units, means responsive to said predetermined signal to advance the phase of one clock signal and retard the phase of the other by a preselected amount to thereby effectively phase reverse said clock signals and reverse the steering of the digroup bit streams, and means for avoiding loss of frame in either receive unit when the steering of the digroup bit streams is reversed.
Claim 2
Dependent Claim
201 words
In a communication system wherein a pair of n-channel digroup signals, each of which includes framing bits, are synchronously multiplexed into a composite signal by bit interleaving the digroup signals, a demultiplexer comprising a pair of gating means to which the composite signal is coupled, means for recovering the timing of said composite signal and for generating therefrom a pair of phase inverted clock signals each at the digroup bit rate, means for respectively coupling said clock signals to said gating means to alternately enable the same and thereby steer the interleaved digroup bits of said composite signal to separate digroup receive units, means for comparing the relative timing of the bits coupled to each of the receive units and for generating a predetermined signal when the digroup bit streams are being sent to the wrong receive units, means responsive to said predetermined signal to advance the phase of one clock signal and retard the phase of the other by a preselected amount to thereby effectively phase reverse said clock signals and reverse the steering of the digroup bit streams, and means for avoiding loss of frame in either receive unit when the steering of the digroup bit streams is reversed.
Claim 3
Dependent Claim
33 words
A demultiplexer as defined in claim 1 wherein each clock signal which steers a digroup bit stream to a given receive unit is cross-coupled as a clock signal to the other receive unit.
Claim 4
Dependent Claim
24 words
A demultiplexer as defined in claim 2 including means for inhibiting the means responsive to said predetermined signal if either receive unit is out-of-frame.
Claim 5
Dependent Claim
17 words
A demultiplexer as defined in claim 1 wherein each of said gating means comprises a D-type flip-flop.
Claim 6
Dependent Claim
31 words
A demultiplexer as defined in claim 4 wherein the timing recovery means comprises a D-type flip-flop with feedback connection means for providing a divide by two operation for the recovered timing.