Demultiplexer circuit

Abstract

Abstract This disclosure relates to a demultiplexer for a pair of digital groups (digroups) which are synchronously multiplexed into a composite signal by bit interleaving the pair. The composite multiplex signal is coupled to each of a pair of gating circuits. A clock recovery circuit recovers the timing of the composite signal and generates therefrom a pair of phase inverted clock signals. These clock signals are respectively coupled to the two gating circuits to alternately enable the same and thereby steer the interleaved digroup bits to separate digroup receive units. A comparison circuit is coupled to each receive unit to compare the relative timing of the bits delivered thereto; this comparison utilizes the fact that multiplexing is done with the bits of one digroup preceding the bits of the other. If the steering is incorrect and the respective digroup bit streams are being sent to the wrong receive units, the comparison circuit generates a signal which serves to phase reverse the clock signals and consequently the enabling of the gating circuits. This reverses, and thereby corrects, the steering of the digroup bit streams.

Inventors

• 👤 Charles R. Crue

Bibliographic Details