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US4093940A Expired / Lapsed US ⏱️ 0.0 years remaining

System and equipment for quality checking of a digital connection circuit

Assignee: Lignes Telegraphiques et Telephoniques LTT SA
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Filing: 1977-02-15
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Granted: 1978-06-06
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Expires: 1997-02-15
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Abstract

Abstract A system for quality checking of a digital connection circuit using a telephone line. Its principle resides in alternately and repetitively transmitting a check message followed by a quality character from one to the other of two similar equipments respectively located at the ends of the circuit. The quality character takes account of the results of the checking effected by the corresponding equipment when it receives the last previously transmitted check message. The latter message further includes a n times repeated synchronization character and a pseudo-random series of p binary signals and is immediately followed by a quality character which is stored and displayed by the receiving equipment which operates at the considered time.

Inventors

  • 👤 Maurice Maniere

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 12:13
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/24

Claims Analysis

Total Claims: 9
Claim 1
Independent Claim 371 words
A system for checking the quality of a digital connection circuit comprising: a first device including transmitting and receiving means connected to the first end of said circuit for respectively transmitting a check message and a quality character sent in a given direction of said circuit under test during transmit cycles assigned to said first device and receiving a check message and a quality character sent in the other direction of said circuit under test during receive cycles assigned to said first device; a second device identical to the first device including transmitting and receiving means connected to the second end of said circuit for respectively transmitting a check message and a quality character sent in said other direction of said circuit under test during transmit cycles assigned to said second device and coinciding with the receive cycles assigned to the first device and receiving a check message and a quality character sent in the given direction of said circuit under test during receive cycles assigned to said second device and coinciding with the transmit cycles assigned to the first device; control units respectively connected to the ends of said digital connection circuit including means for periodically switching said first and second devices to thereby reverse transmission and reception; each of said control units including means for respectively generating, transmitting and receiving a synchronization character having i bits repeated n times and forming the first part of said check message and further including means for respectively generating, transmitting and receiving a pseudo-random sequence of p bits, forming the second part of said check message, each covering one further bit interval immediately following said synchronization character; store means connected to said control units for storing said received synchronization character, pseudo-random sequence and quality character; error detector means and coding means connected to said store means, deriving from the errors in said received synchronization characters and pseudo-random sequence a coded result forming the quality character; display means for displaying the quality character received in each of said device during the receive cycle wherein it is received; and means for adding said quality character to the check message transmitted by each of said device during the transmit cycle following that wherein it is received.
Claim 2
Independent Claim 371 words
A system for checking the quality of a digital connection circuit comprising: a first device including transmitting and receiving means connected to the first end of said circuit for respectively transmitting a check message and a quality character sent in a given direction of said circuit under test during transmit cycles assigned to said first device and receiving a check message and a quality character sent in the other direction of said circuit under test during receive cycles assigned to said first device; a second device identical to the first device including transmitting and receiving means connected to the second end of said circuit for respectively transmitting a check message and a quality character sent in said other direction of said circuit under test during transmit cycles assigned to said second device and coinciding with the receive cycles assigned to the first device and receiving a check message and a quality character sent in the given direction of said circuit under test during receive cycles assigned to said second device and coinciding with the transmit cycles assigned to the first device; control units respectively connected to the ends of said digital connection circuit including means for periodically switching said first and second devices to thereby reverse transmission and reception; each of said control units including means for respectively generating, transmitting and receiving a synchronization character having i bits repeated n times and forming the first part of said check message and further including means for respectively generating, transmitting and receiving a pseudo-random sequence of p bits, forming the second part of said check message, each covering one further bit interval immediately following said synchronization character; store means connected to said control units for storing said received synchronization character, pseudo-random sequence and quality character; error detector means and coding means connected to said store means, deriving from the errors in said received synchronization characters and pseudo-random sequence a coded result forming the quality character; display means for displaying the quality character received in each of said device during the receive cycle wherein it is received; and means for adding said quality character to the check message transmitted by each of said device during the transmit cycle following that wherein it is received.
Claim 3
Independent Claim 346 words
A method for checking the quality of a digital connection circuit provided with a first and a second devices connected to the ends thereof having means for alternately transmitting and receiving a check message and a quality character on the circuit under test said method comprising the following steps: (1) alternately generating in each of said devices acting as a transmitter device a synchronization character having i bits repeated n times and forming the first part of said check message, a predetermined subsequent pseudo-random sequence of p bits forming the second part of said check message and a quality character incorporated at the end of the said check message; (2) alternately receiving in each of said devices acting as a receiver device said repeated synchronization character, said transmitted subsequent pseudo-random sequence and said quality character; (3) identifying in identifying means connected to said first and second devices the non faulty synchronization characters in the check message received in each of said devices; (4) counting in first counter means connected to said identifying means the number of the non faulty synchronization characters identified in step (3); (5) coding in first coder means connected to said first counting means the number of the non faulty identified synchronization characters counted in step (4); (6) storing the result of said first coding in step (5); (7) comparing in comparator means connected to said first and second devices the received pseudo-random sequence to the predetermined pseudo-random sequence; (8) counting in second counting means connected to said comparator means the number of identical bits resulting from comparison in step (7); (9) coding in second coding means connected to said second counting means the number of the identical bits counted in step (8); (10) storing the result of said second coding in step (9) beside the result of said first coding to form the quality character; (11) displaying said quality character in the device wherein it is stored and adding the quality factor to the check message at the end thereof to be forwarded to the other device together with said check message.
Claim 4
Independent Claim 346 words
A method for checking the quality of a digital connection circuit provided with a first and a second devices connected to the ends thereof having means for alternately transmitting and receiving a check message and a quality character on the circuit under test said method comprising the following steps: (1) alternately generating in each of said devices acting as a transmitter device a synchronization character having i bits repeated n times and forming the first part of said check message, a predetermined subsequent pseudo-random sequence of p bits forming the second part of said check message and a quality character incorporated at the end of the said check message; (2) alternately receiving in each of said devices acting as a receiver device said repeated synchronization character, said transmitted subsequent pseudo-random sequence and said quality character; (3) identifying in identifying means connected to said first and second devices the non faulty synchronization characters in the check message received in each of said devices; (4) counting in first counter means connected to said identifying means the number of the non faulty synchronization characters identified in step (3); (5) coding in first coder means connected to said first counting means the number of the non faulty identified synchronization characters counted in step (4); (6) storing the result of said first coding in step (5); (7) comparing in comparator means connected to said first and second devices the received pseudo-random sequence to the predetermined pseudo-random sequence; (8) counting in second counting means connected to said comparator means the number of identical bits resulting from comparison in step (7); (9) coding in second coding means connected to said second counting means the number of the identical bits counted in step (8); (10) storing the result of said second coding in step (9) beside the result of said first coding to form the quality character; (11) displaying said quality character in the device wherein it is stored and adding the quality factor to the check message at the end thereof to be forwarded to the other device together with said check message.
Claim 5
Independent Claim 429 words
A system for checking the quality of a digital connection circuit comprising: a first device incluing a modem connected to the first end of said circuit, transmitting and receiving means connected to said modem for respectively transmitting through said modem a check message and a quality character sent in a given direction of said circuit under test during transmit cycles assigned to said first device and receiving through said modem a check message and a quality character sent in the other direction of said circuit under test during receive cycles assigned to said first device; a second device identical to the first device including a modem connected to the second end of said circuit, transmitting and receiving means connected to the second end of said circuit for respectively transmitting through said modem a check message and a quality character sent in said other direction of said circuit under test during transmit cycles assigned to said second device and coinciding with the receive cycles assigned to the first device and receiving through said modem a check message and a quality character sent in the given direction of said circuit under test during receive cycles assigned to said second device and coinciding with the transmit cycles assigned to the first device; control units respectively connected to the ends of said digital connection circuit each including a transmission bit interval generator controlling the modem, a reception bit interval generator controlled by the modem, a synchronization character generator, a faulty synchronization character detector and counter, a pseudo-random sequence generator, a pseudo-random sequence error detector, a quality character forming circuit, a quality character display means, a coding circuit having its inputs connected to said faulty synchronization character detector and counter and to said pseudo-random sequence error detector and its output to said quality character forming circuit, means controlled by said transmission bit interval generator for sequentially connecting to the modem during a transmit cycle the synchronization character generator from bit interval No. 0 to bit interval No. (ni-1), the pseudo-random sequence generator from bit interval No. ni to bit interval No. (ni+p-1) and the quality character forming circuit from bit interval No. ni+p to bit interval [(n+1) i+p-1], means controlled by said reception bit interval generator for connecting to the modem during a receive cycle the faulty synchronization character detector and counter from bit interval No. 0 to bit interval No. (ni-1), the pseudo-random sequence error detector from bit interval No. ni to bit interval No. (ni+p-1) and the quality character display means from bit interval No. (ni+p) to bit interval No. [(n+1)i+ p-1].
Claim 6
Independent Claim 429 words
A system for checking the quality of a digital connection circuit comprising: a first device incluing a modem connected to the first end of said circuit, transmitting and receiving means connected to said modem for respectively transmitting through said modem a check message and a quality character sent in a given direction of said circuit under test during transmit cycles assigned to said first device and receiving through said modem a check message and a quality character sent in the other direction of said circuit under test during receive cycles assigned to said first device; a second device identical to the first device including a modem connected to the second end of said circuit, transmitting and receiving means connected to the second end of said circuit for respectively transmitting through said modem a check message and a quality character sent in said other direction of said circuit under test during transmit cycles assigned to said second device and coinciding with the receive cycles assigned to the first device and receiving through said modem a check message and a quality character sent in the given direction of said circuit under test during receive cycles assigned to said second device and coinciding with the transmit cycles assigned to the first device; control units respectively connected to the ends of said digital connection circuit each including a transmission bit interval generator controlling the modem, a reception bit interval generator controlled by the modem, a synchronization character generator, a faulty synchronization character detector and counter, a pseudo-random sequence generator, a pseudo-random sequence error detector, a quality character forming circuit, a quality character display means, a coding circuit having its inputs connected to said faulty synchronization character detector and counter and to said pseudo-random sequence error detector and its output to said quality character forming circuit, means controlled by said transmission bit interval generator for sequentially connecting to the modem during a transmit cycle the synchronization character generator from bit interval No. 0 to bit interval No. (ni-1), the pseudo-random sequence generator from bit interval No. ni to bit interval No. (ni+p-1) and the quality character forming circuit from bit interval No. ni+p to bit interval [(n+1) i+p-1], means controlled by said reception bit interval generator for connecting to the modem during a receive cycle the faulty synchronization character detector and counter from bit interval No. 0 to bit interval No. (ni-1), the pseudo-random sequence error detector from bit interval No. ni to bit interval No. (ni+p-1) and the quality character display means from bit interval No. (ni+p) to bit interval No. [(n+1)i+ p-1].
Claim 7
Dependent Claim 28 words
A system for checking the quality of a digital connection circuit as claimed in claim 1 in which n = 4, i = 8 and p = 512
Claim 8
Dependent Claim 56 words
A system for checking the quality of a digital connection circuit as claimed in claim 1 further comprising means for disconnecting the control units from the ends of said digital connection circuit when the receiving means of a device receives a predetermined number of consecutive check messages deprived of a quality character at the end thereof.
Claim 9
Dependent Claim 53 words
A system for checking the quality of a digital connection circuit as claimed in claim 3 wherein said transmission bit interval generator and said reception bit interval generator comprise reset to zero means modulo 2p for controlling the means for periodically switching the first and second devices to thereby reverse transmission and reception.

References Cited (Backward Citations)

US3315228A Cited
US3496536A Cited
US3491338A Cited
US3596245A Cited
US3760354A Cited
USB394088I5 Cited
US3904861A Cited
US4022988A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1981-06-05 1981-12-05 1982-06-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1985-06-05 1985-12-05 1986-06-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1989-06-05 1989-12-05 1990-06-06 $7700.00 Window Closed / Lapsed

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