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US4093909A Expired / Lapsed US ⏱️ 0.0 years remaining

Method and apparatus for operating a semiconductor integrated circuit at minimum power requirements

Assignee: General Electric Co
•
Filing: 1976-07-21
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Granted: 1978-06-06
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Expires: 1996-07-21
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Abstract

Abstract A method and apparatus for operating a smiconductor integrated circuit at minimum power from a voltage source, including deriving a semiconductor process parameter dependent reference voltage within the integrated circuit, comparing the magnitude of the reference voltage and the voltage source and maintaining the magnitude of the voltage source greater than the reference voltage.

Inventors

  • 👤 Donald L. Watrous
  • 👤 Daniel W. Dobberphul

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-24 22:07
CPC Classifications
G; G05; G05F; G05F1/00; G05F1/10; G05F1/46; G05F1/613; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/24; G05F3/242

Claims Analysis

Total Claims: 12
Claim 1
Independent Claim 71 words
A method for operating a semiconductor integrated circuit at minimum power requirements from a voltage source, said method comprising: deriving a semiconductor integrated circuit process parameter dependent reference voltage from said integrated circuit; comparing the magnitudes of said reference voltage and said voltage source; and maintaining the magnitude of the voltage to said integrated circuit at a minimum value required for reliable circuit operation with minimum power consumption in said circuit.
Claim 2
Independent Claim 71 words
A method for operating a semiconductor integrated circuit at minimum power requirements from a voltage source, said method comprising: deriving a semiconductor integrated circuit process parameter dependent reference voltage from said integrated circuit; comparing the magnitudes of said reference voltage and said voltage source; and maintaining the magnitude of the voltage to said integrated circuit at a minimum value required for reliable circuit operation with minimum power consumption in said circuit.
Claim 3
Dependent Claim 54 words
The method of claim 1 wherein said voltage source includes a battery and a converter charging a capacitor and the step of maintaining the magnitude of the voltage to said integrated circuit comprises: operating said converter in an ON/OFF mode to charge said capacitor and increase the voltage thereon greater than said reference voltage.
Claim 4
Dependent Claim 28 words
The method of claim 2 wherein said reference voltage is derived from current flowing through a voltage divider including a pair of serially connected enhancement mode field-effect transistors.
Claim 5
Dependent Claim 27 words
The method of claim 2 wherein the step of operating said converter includes: controlling the frequency of said converter by the ON/OFF switching rate of a transistor.
Claim 6
Dependent Claim 25 words
The method of claim 4 further comprising the step of: regulating the magnitude of the voltage applied to other semiconductor devices in said integrated circuit.
Claim 7
Dependent Claim 125 words
In combination a semiconductor integrated circuit adapted to be powered from a battery and a converter having a charge storage capacitor for providing a filtered DC voltage to said circuit, the improvement comprising: voltage divider means in said integrated circuit for providing a semiconductor integrated circuit process parameter dependent reference voltage; comparator means for comparing the magnitudes of said reference voltage and said filtered DC voltage, said comparator means providing an output control signal indicative of the relative magnitudes of said voltages; and switching means operatively connected to said output control signal for enabling said converter to charge said capacitor and maintain the magnitude of said DC voltage at the minimum value required for reliable circuit operation with minimum power consumption in the integrated circuit.
Claim 8
Dependent Claim 125 words
In combination a semiconductor integrated circuit adapted to be powered from a battery and a converter having a charge storage capacitor for providing a filtered DC voltage to said circuit, the improvement comprising: voltage divider means in said integrated circuit for providing a semiconductor integrated circuit process parameter dependent reference voltage; comparator means for comparing the magnitudes of said reference voltage and said filtered DC voltage, said comparator means providing an output control signal indicative of the relative magnitudes of said voltages; and switching means operatively connected to said output control signal for enabling said converter to charge said capacitor and maintain the magnitude of said DC voltage at the minimum value required for reliable circuit operation with minimum power consumption in the integrated circuit.
Claim 9
Dependent Claim 48 words
The combination of claim 6 wherein said voltage divider means includes a pair of enhancement mode field-effect transistors serially connected together and to a plurality of depletion mode field-effect transistors serially connected together, the threshold voltages of said enhancement mode field-effect transistors providing said process parameter dependent voltage.
Claim 10
Dependent Claim 40 words
The combination of claim 7 wherein said switching means includes: an oscillator; a logic gate enabled by said output control signal and operatively connected to said oscillator for enabling said oscillator to control the frequency of operation of said converter.
Claim 11
Dependent Claim 32 words
The combination of claim 8 wherein said converter operates in an ON/OFF burst mode as controlled by said logic gate to charge said capacitor to the voltage required by said integrated circuit.
Claim 12
Dependent Claim 26 words
The combination of claim 9 further comprising a shunt regulator operatively connected to said DC voltage and controlled by a signal from said voltage divider means.

References Cited (Backward Citations)

SU242982A1 Cited
US3508084A Cited
US3832644A Cited
US3913026A Cited
US4020367A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1981-06-05 1981-12-05 1982-06-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1985-06-05 1985-12-05 1986-06-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1989-06-05 1989-12-05 1990-06-06 $7700.00 Window Closed / Lapsed

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