Bit error rate performance monitor units in digital transmission links

Claim 2

A bit error rate performance monitor unit for use in a digital transmission link having a receiving end and an operative output end, comprising first and second demodulators having substantially the same structure, means connecting the receiving end of said data transmission link to the inputs of said demodulators, means connecting the operative output end to the output of said first demodulator, a module-2 adder having its inputs respectively connected to the outputs of said demodulators, a counter connected to the output of said adder, and means reproducibly disturbing the operation of said second demodulator, whereby the bit error rate can be determined from the counter reading divided by the operation period.

Claim 3

A bit error rate performance monitor unit according to claim 1, in which the means disturbing the operation of said second demodulator reduces the slope of the bit error rate curve as a function of the signal-to-noise ratio.

Claim 4

A bit error rate performance monitor unit according to claim 1 in which the means reproducibly disturbing the operation of said second demodulator comprises a generator and means injecting the output of said generator between the receiving end of said transmission link and the input of said second demodulator.

Claim 5

A bit error rate performance monitor unit according to claim 3, in which said generator delivers a pure carrier whose frequency lies within the digital transmission link frequency band.

Claim 6

A bit error rate performance monitor unit according to claim 3, in which said generator delivers a modulated carrier whose frequency lies within the digital transmission link frequency band.

Claim 7

A bit error rate performance monitor unit according to claim 1, in which the means reproducibly disturbing the operation of said second demodulator comprises a filter having a wider pass band, serially connected between the receiving end of said transmission link and the input of said second demodulator.

Claim 8

A bit error rate performance monitor unit according to claim 1, in which the means reproducibly disturbing the operation of said second demodulator comprises a delay circuit connected to the receiving end of said transmission link, an attenuator connected to the output of said delay circuit, and means connected to the input of said second demodulator adding the output of the receiving end of said transmission link to the output of said attenuator.

Claim 9

A bit error rate performance monitor unit for use in a digital phase-modulated transmission link having a receiving end and an operative output, comprising substantially identical first and second demodulators, each of which includes an operative digital clock regenerator circuit, means connecting the receiving end of said data transmission link to the inputs of said demodulators, means connecting the operative output end to the output of said first demodulator, a module-2 adder having its inputs respectively connected to the outputs of said demodulators, a counter connected to the output of said adder, and means comprising a phase shifter connected between th output of the digital clock regenerator and the output of said second demodulator for reproducibly disturbing the operation of said second demodulator, whereby the bit error rate can be determined from the counter reading divided by the operation period.

Claim 10

A bit error rate performance monitor unit for use in a digital phase-modulated transmission link having a receiving end and an operative output, comprising substantially identical first and second demodulators, each of which includes an operative digital clock regenerator circuit, means connecting the receiving end of said data transmission link to the inputs of said demodulators, means connecting the operative output end to the output of said first demodulator, a module-2 adder having its inputs respectively connected to the outputs of said demodulators, a counter connected to the output of said adder, and means comprising a phase shifter connected between th output of the digital clock regenerator and the output of said second demodulator for reproducibly disturbing the operation of said second demodulator, whereby the bit error rate can be determined from the counter reading divided by the operation period.

Claim 11

A bit error rate performance monitor unit for use in a digital phase-modulated transmission link having a receiving end and an operative output end comprising substantially identical first and second coherent demodulators each of which includes a carrier regeneration circuit providing a carrier frequency in the coherent demodulation operation, means connecting the receiving end of said data transmission link to the inputs of said demodulators, means connecting the operative output end to the output of said first demodulator, a module-2 adder having its inputs respectively connected to the outputs of said demodulators, a counter connected to the output of said adder and means comprising a phase shifter connected to the output of the carrier regeneration circuit of said second demodulator for reproducibly disturbing the operation of said second demodulator, whereby the bit error rate can be determined from the counter reading divided by the operation period.

Claim 12

A bit error rate performance monitor unit for use in a digital phase-modulated transmission link having a receiving end and an operative output end comprising substantially identical first and second coherent demodulators each of which includes a carrier regeneration circuit providing a carrier frequency in the coherent demodulation operation, means connecting the receiving end of said data transmission link to the inputs of said demodulators, means connecting the operative output end to the output of said first demodulator, a module-2 adder having its inputs respectively connected to the outputs of said demodulators, a counter connected to the output of said adder and means comprising a phase shifter connected to the output of the carrier regeneration circuit of said second demodulator for reproducibly disturbing the operation of said second demodulator, whereby the bit error rate can be determined from the counter reading divided by the operation period.

Claim 13

A bit error rate performance monitor unit for use in a digital phase-modulated transmission link having a receiving end and an operative output end, comprising substantially identical first and second differential demodulators each including a delay line providing a delay time corresponding to the time interval between two bits, means connecting the receiving end of said data transmission link to the inputs of said demodulators, means connecting the operative end to the output of said first demodulator, a module-2 adder having its inputs respectively connected to the outputs of said demodulators, a counter connected to the output of said adder, and means adjusting the delay time of said second demodulator relative to the delay time of said first demodulator for reproducibly disturbing the operation of said second demodulator, whereby the bit error rate can be determined from the counter reading divided by the operation period.

Claim 14

A bit error rate performance monitor unit for use in a digital phase-modulated transmission link having a receiving end and an operative output end, comprising substantially identical first and second differential demodulators each including a delay line providing a delay time corresponding to the time interval between two bits, means connecting the receiving end of said data transmission link to the inputs of said demodulators, means connecting the operative end to the output of said first demodulator, a module-2 adder having its inputs respectively connected to the outputs of said demodulators, a counter connected to the output of said adder, and means adjusting the delay time of said second demodulator relative to the delay time of said first demodulator for reproducibly disturbing the operation of said second demodulator, whereby the bit error rate can be determined from the counter reading divided by the operation period.