Patent US4091239A successfully refreshed from Google Patents.
US4091239A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Bit error rate performance monitor units in digital transmission links
Assignee: Individual
•
Filing: 1977-03-15
•
Granted: 1978-05-23
•
Expires: 1997-03-15
Abstract
Abstract A bit error performance monitor in which the input signal is equally shared by two substantially identical monitors whose outputs in turn are connected to an adder. The output of the adder passes through a divider-by-2 to a counter.
Inventors
- 👤 Gilbert P. Lainey
- 👤 Jean-Claude A. Imbeaux
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:58
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/24; H04L1/241
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
110 words
A bit error rate performance monitor unit for use in a digital transmission link having a receiving end and an operative output end comprising first and second demodulators having substantially the same structure, means connecting the receiving end of said data transmission link to the inputs of said demodulators, means connecting the operative output end to the output of said first demodulator, a module-2 adder having its inputs respectively connected to the outputs of said demodulators, a counter, and a divider-by-2 interconnecting the output of said adder with the input of said counter, whereby the bit error rate can be determined from the counter reading divided by the operation period.
Claim 2
Dependent Claim
110 words
A bit error rate performance monitor unit for use in a digital transmission link having a receiving end and an operative output end comprising first and second demodulators having substantially the same structure, means connecting the receiving end of said data transmission link to the inputs of said demodulators, means connecting the operative output end to the output of said first demodulator, a module-2 adder having its inputs respectively connected to the outputs of said demodulators, a counter, and a divider-by-2 interconnecting the output of said adder with the input of said counter, whereby the bit error rate can be determined from the counter reading divided by the operation period.
Claim 3
Independent Claim
62 words
The method of monitoring the bit error rate performance of a digital transmission link, comprising the steps of passing the received signals simultaneously and equally through two demodulators having substantially identical characteristics, adding the outputs of the two demodulators by a module-2 adding operation, dividing by 2 the results of such addition, and measuring the bit error rate resulting from such division.
Claim 4
Independent Claim
62 words
The method of monitoring the bit error rate performance of a digital transmission link, comprising the steps of passing the received signals simultaneously and equally through two demodulators having substantially identical characteristics, adding the outputs of the two demodulators by a module-2 adding operation, dividing by 2 the results of such addition, and measuring the bit error rate resulting from such division.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-05-22 | 1981-11-21 | 1982-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-05-22 | 1985-11-21 | 1986-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-05-22 | 1989-11-21 | 1990-05-23 | $7700.00 | Window Closed / Lapsed |