Patent US4090244A successfully refreshed from Google Patents.
US4090244A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method and circuit arrangement for determining the vector components of an oscillation
Assignee: Carl Schenck AG
•
Filing: 1977-03-04
•
Granted: 1978-05-16
•
Expires: 1997-03-04
Abstract
Abstract A method for determining a vector component of an oscillation such as an oscillatory signal comprises applying the measured analog oscillatory signal to the calibration voltage input of a multiplying digital-to-analog (D/A) converter, and simultaneously applying a digital reference signal to the digital input of the digital-to-analog converter. The reference signal includes sine or cosine values of an oscillation suitable for the vector component determination and having a frequency corresponding to the frequency of the oscillatory signal to be determined. The analog output of the D/A converter is then further processed to ascertain the desired vector component. The circuit arrangement for practicing this method comprises a multiplying digital-to-analog converter and a binary counter which sequentially addresses a digital memory used to provide the digital reference signals. The binary counter is controlled by a reference signal generator.
Inventors
- 👤 Michael Altwein
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:50
CPC Classifications
G; G01; G01M; G01M1/00; G01M1/14; G01M1/16; G01M1/22; G01M1/225; G06; G06F; G06F7/00; G06F7/60; G06F7/62; G06J; G06J1/00
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
199 words
A circuit arrangement for extracting required analog output signals from an analog oscillatory input signal to determine the vector components of said input signal which includes a mixture of interfering signals having different frequencies and amplitudes, comprising a first source for supplying said analog input signals, and a second source for supplying digital reference signal, a multiplying digital-to-analog converter having a plurality of digital input means and analog input means, as well as output means, said first source of analog input signals being connected to said analog input means of said D/A converter, said circuit arrangement further comprising digital memory means having addressing inputs and control outputs and binary counter means having input means connected to said second source for supplying said digital reference signals to said binary counter means, said binary counter means having output means connected to said addressing inputs of said digital memory means, said control outputs of said digital memory means being connected to said digital input means of said D/A converter, whereby a multiplying signal combination is provided in said D/A converter in response to the addressing and stepping of said digital memory by said binary counter in response to said digital reference signals.
Claim 2
Dependent Claim
199 words
A circuit arrangement for extracting required analog output signals from an analog oscillatory input signal to determine the vector components of said input signal which includes a mixture of interfering signals having different frequencies and amplitudes, comprising a first source for supplying said analog input signals, and a second source for supplying digital reference signal, a multiplying digital-to-analog converter having a plurality of digital input means and analog input means, as well as output means, said first source of analog input signals being connected to said analog input means of said D/A converter, said circuit arrangement further comprising digital memory means having addressing inputs and control outputs and binary counter means having input means connected to said second source for supplying said digital reference signals to said binary counter means, said binary counter means having output means connected to said addressing inputs of said digital memory means, said control outputs of said digital memory means being connected to said digital input means of said D/A converter, whereby a multiplying signal combination is provided in said D/A converter in response to the addressing and stepping of said digital memory by said binary counter in response to said digital reference signals.
Claim 3
Dependent Claim
58 words
The circuit arrangement of claim 1, further comprising inverter circuit means connected to said D/A converter output means, said binary counter means having further output means connected to said inverter circuit means for switching the inverter circuit means to invert the output signal of said D/A converter in response to a predetermined count in said binary counter means.
Claim 4
Dependent Claim
32 words
The circuit arrangement of claim 1, wherein said binary counter means comprises a presettable counter which may be preset to any desired start counting position out of a plurality of such positions.
Claim 5
Independent Claim
123 words
A method for extracting required analog output signals from an oscillatory analog input signal to determine the vector components of said input signal which includes a mixture of interfering signals having different frequencies and amplitudes comprising applying said oscillatory input signal to the analog input of a multiplying digital-to-analog converter, producing a digital reference signal corresponding to sine or cosine values of a reference oscillation suitable for said determining of vector components, said digital reference signal having a frequency corresponding to the frequency of said oscillatory, analog input signal, and applying said digital reference signal to the digital input means of said digital-to-analog converter, and then using the analog output signal of said digital-to-analog converter for further processing to determine said vector components.
Claim 6
Independent Claim
123 words
A method for extracting required analog output signals from an oscillatory analog input signal to determine the vector components of said input signal which includes a mixture of interfering signals having different frequencies and amplitudes comprising applying said oscillatory input signal to the analog input of a multiplying digital-to-analog converter, producing a digital reference signal corresponding to sine or cosine values of a reference oscillation suitable for said determining of vector components, said digital reference signal having a frequency corresponding to the frequency of said oscillatory, analog input signal, and applying said digital reference signal to the digital input means of said digital-to-analog converter, and then using the analog output signal of said digital-to-analog converter for further processing to determine said vector components.
Claim 7
Dependent Claim
24 words
The method of claim 4, further comprising sequentially addressing a memory to produce said sine or cosine reference values of said digital reference signal.
Claim 8
Dependent Claim
29 words
The method of claim 5, further comprising deriving the digital cosine reference values from the digital sine reference values by applying a phase shift to the sine reference values.
Claim 9
Dependent Claim
34 words
The method of claim 5, wherein said digital reference values are retrieved from said memory by using a binary count for said sequential addressing to control the operation of said D/A-converter through said memory.
Claim 10
Dependent Claim
43 words
The method of claim 7, wherein said binary count steps the digital memory in such a manner that the addresses of the digital memory are scanned several times during one period of the oscillation, the vector components of which are to be ascertained.
Claim 11
Dependent Claim
27 words
The method of claim 7, further comprising producing any desired phase position for the reference values by preselecting fixed addresses or counting positions in the binary counter.
Claim 12
Dependent Claim
27 words
The method of claim 7, further comprising inverting the output signal of the digital-to-analog converter in response to a predetermined counting position of the addressing binary counter.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-05-15 | 1981-11-14 | 1982-05-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-05-15 | 1985-11-14 | 1986-05-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-05-15 | 1989-11-14 | 1990-05-16 | $7700.00 | Window Closed / Lapsed |