Complementary symmetry FET mixer circuits

Claim 2

A mixer comprising, in combination: first and second terminals between which an operating voltage may be applied; a circuit output terminal; six field effect transistors, first and second and third of these transistors being of a first conductivity type and fourth and fifth and sixth of these transistors being of a second conductivity type complementary to said first conductivity type, each transistor having a conduction path between input and output electrodes and having a control electrode, the conduction paths of said first and second and third transistors being serially connected between said first terminal and said output terminal, and the conduction paths of said fourth and fifth and sixth transistors being serially connected between said second terminal and said output terminal; means for quiescently biasing all of said transistors in the linear region of their operating range including: means for applying similar quiescent potentials to the control electrodes of said first and fourth transistors thereby to connect them as a first complementary conduction pair, means for applying similar quiescent potentials to the control electrodes of said second and fifth transistors thereby to connect them as a second complementary conduction pair, and means for applying similar quiescent potentials to the control electrodes of said third and sixth transistors, thereby to connect them as a third complementary conduction pair; means for applying a first input signal at frequency f 1 to the control electrodes of said first and fourth transistors; means for applying a second input signal at frequency f 2 to the control electrodes of said second and fifth transistors; and a tuned output circuit coupled between said output terminal and another circuit point, said circuit being tuned to the one of the output signal frequency components of interest available at said output terminal.

Claim 3

A mixer as set forth in claim 1, wherein said third and sixth transistors are connected at their output electrodes to said output terminal and at their control electrodes to a point of alternating current ground.

Claim 4

A mixer as set forth in claim 1, wherein said third and sixth transistors are connected at their output electrodes to said output terminal, and further including: means for applying a signal at a third frequency to the control electrodes of said third and sixth transistors.

Claim 5

A mixer as set forth in claim 1, wherein said means for applying similar quiescent potentials to the control electrodes of said first and fourth transistors comprises first resistive means connected between said output terminal and the control electrodes of said first and fourth transistors, said means for applying similar quiescent potentials to the control electrodes of said second and fifth transistors comprises second resistive means connected between said output terminal and the control electrodes of said second and fifth transistors, and said means for applying similar quiescent potentials to the control electrodes of said third and sixth transistors comprises third resistive means connected between said output terminal and the control electrodes of said third and sixth transistors.

Claim 6

A mixer comprising, in combination: first and second terminals between which an operating voltage may be applied; a circuit output terminal; six MOS transistors, the first and second and third of P-type and the fourth and fifth and sixth of N-type, each transistor having a conduction path between source and drain electrodes and having a gate electrode, the conduction paths of the first and second and third transistors being serially connected between said first terminal and said output terminal, and the conduction paths of the fourth and fifth and sixth transistors being serially connected between said second terminal and said output terminal; means for quiescently biasing the gate electrodes of the first and fourth transistors at a voltage level such that each operates in the linear region of its operating range whereby the first and fourth transistors operate as a first complementary conduction pair; means for quiescently biasing the gate electrode of said second and fifth transistors at a voltage level such that each operates in the linear region of its operating range, whereby the second and fifth transistors operate as a second complementary conduction pair; means for quiescently biasing the gate electrodes of said third and sixth transistors at a voltage level such that each operates in the linear region of its operating range, whereby the third and sixth transistors operate as a third complementary conduction pair; a first parallel tuned circuit, tuned to frequency f 1 , connected at one terminal to AC ground and at its other terminal to the gate electrodes of said first and fourth transistors; means for introducing a signal at frequency f 1 to said first circuit; a second parallel tuned circuit, this one tuned to frequency f 2 , connected at one terminal to AC ground and at its other terminal to the gate electrodes of said second and fifth transistors; means for introducing a signal at frequency f 2 to said second circuit; and a third parallel tuned circuit tuned to one of the frequency components present at said output terminal connected between said output terminal and AC ground.

Claim 7

A mixer comprising, in combination: first and second terminals between which an operating voltage may be applied; a circuit output terminal; six MOS transistors, the first and second and third of P-type and the fourth and fifth and sixth of N-type, each transistor having a conduction path between source and drain electrodes and having a gate electrode, the conduction paths of the first and second and third transistors being serially connected between said first terminal and said output terminal, and the conduction paths of the fourth and fifth and sixth transistors being serially connected between said second terminal and said output terminal; means for quiescently biasing the gate electrodes of the first and fourth transistors at a voltage level such that each operates in the linear region of its operating range whereby the first and fourth transistors operate as a first complementary conduction pair; means for quiescently biasing the gate electrode of said second and fifth transistors at a voltage level such that each operates in the linear region of its operating range, whereby the second and fifth transistors operate as a second complementary conduction pair; means for quiescently biasing the gate electrodes of said third and sixth transistors at a voltage level such that each operates in the linear region of its operating range, whereby the third and sixth transistors operate as a third complementary conduction pair; a first parallel tuned circuit, tuned to frequency f 1 , connected at one terminal to AC ground and at its other terminal to the gate electrodes of said first and fourth transistors; means for introducing a signal at frequency f 1 to said first circuit; a second parallel tuned circuit, this one tuned to frequency f 2 , connected at one terminal to AC ground and at its other terminal to the gate electrodes of said second and fifth transistors; means for introducing a signal at frequency f 2 to said second circuit; and a third parallel tuned circuit tuned to one of the frequency components present at said output terminal connected between said output terminal and AC ground.

Claim 8

A mixer as set forth in claim 5, further including: means connecting the gate electrodes of said third and sixth transistors to AC ground.

Claim 9

A mixer as set forth in claim 5, further including: a fourth parallel tuned circuit, this one tuned to frequency f 3 , connected at one terminal to AC ground and at its other terminal to the gate electrodes of said third and sixth transistors.

Claim 10

A mixer as set forth in claim 1 wherein the conduction paths of said first and second and third transistors are serially connected in order of their numbering between said first terminal and said output terminal and wherein the conduction paths of said fourth and fifth and sixth transistors are serially connected in order of their numbering between said second terminal and said output terminal.

Claim 11

A mixer as set forth in claim 5 wherein the conduction paths of said first and second and third transistors are serially connected in order of their numbering between said first terminal and said output terminal and wherein the conduction paths of said fourth and fifth and sixth transistors are serially connected in order of their numbering between said second terminal and said output terminal.

Claim 12

A mixer comprising, in combination: first and second terminals between which an operating voltage may be applied; a circuit output terminal; first and second field effect transistors of a first conductivity type having respective conduction paths in a series connection between said first terminal and said output terminal and having respective gate electrodes; third and fourth field effect transistors of a second conductivity type having respective conduction paths in a series connection between said second terminal and said output terminal and having respective gate electrodes, said first and said second conductivity types being complementary to each other; means for quiescently biasing said first and second and third and fourth transistors in the linear region of their operating range including means for applying similar quiescent potentials to the gate electrodes of said first and third transistors thereby to connect them as a first complementary conductivity pair, and means for applying similar quiescent potentials to the control electrodes of said second and fourth transistors thereby to connect them as a second complementary conduction pair; means for applying a first input signal at frequency f 1 to the gate electrodes of said first and third transistors; means for applying a second input signal at frequency f 2 to the gate electrodes of said second and fourth transistors; and an output circuit coupled between said output terminal and said circuit point, for selecting one of the sum and difference frequencies of f 1 and f 2 available responsive to f 1 and f 2 .

Claim 13

A mixer comprising, in combination: first and second terminals between which an operating voltage may be applied; a circuit output terminal; first and second field effect transistors of a first conductivity type having respective conduction paths in a series connection between said first terminal and said output terminal and having respective gate electrodes; third and fourth field effect transistors of a second conductivity type having respective conduction paths in a series connection between said second terminal and said output terminal and having respective gate electrodes, said first and said second conductivity types being complementary to each other; means for quiescently biasing said first and second and third and fourth transistors in the linear region of their operating range including means for applying similar quiescent potentials to the gate electrodes of said first and third transistors thereby to connect them as a first complementary conductivity pair, and means for applying similar quiescent potentials to the control electrodes of said second and fourth transistors thereby to connect them as a second complementary conduction pair; means for applying a first input signal at frequency f 1 to the gate electrodes of said first and third transistors; means for applying a second input signal at frequency f 2 to the gate electrodes of said second and fourth transistors; and an output circuit coupled between said output terminal and said circuit point, for selecting one of the sum and difference frequencies of f 1 and f 2 available responsive to f 1 and f 2 .

Claim 14

A mixer as set forth in claim 10 including fifth and sixth field effect transistors of said first and said second conductivity types, respectively, each having a gate electrode and a conduction path, the conduction path of said fifth field effect transistor being included in said series connection between said first terminal and said output terminal in the position closest to said output terminal, the conduction path of said sixth field effect transistor being included in said series connection between said second terminal and said output terminal in the position closest to said output terminal; and means for applying similar quiescent potentials to the gate electrodes of said fifth and said sixth transistors thereby to connect them as a third complementary conduction pair.

Claim 15

A mixer as set forth in claim 11 wherein said means for applying similar quiescent potentials to the gate electrodes of said fifth and sixth transistors includes a resistance connected between said output terminal and an interconnection between the gate electrodes of said fifth and sixth transistors, and includes: a capacitance connected between said interconnection between the gate electrodes of said fifth and sixth transistors and one of said first and second terminals.

Claim 16

A mixer as set forth in claim 10 wherein said means for applying similar quiescent potentials to the gate electrodes of said first and third transistors includes a first resistance having a first end connected to said output terminal and having a second end, a first capacitor connecting the second end of said first resistance to one of said first and second terminals, and a first inductor connecting the second end of said first resistance and an interconnection between the gate electrodes of said first and third transistors.

Claim 17

A mixer as set forth in claim 13 wherein said means for applying similar quiescent potentials to the gate electrodes of said second and fourth transistors includes a second resistance having a first end connected to said output terminal and having a second end, a second capacitor connecting the second end of said first resistance to one of said first and second terminals, and a second inductor connecting the second end of said second resistance and an interconnection between the gate electrodes of said second and fourth transistors.

Claim 18

A cascode configuration comprising: means for supplying an input signal potential; first and second terminals for receiving an operating voltage therebetween; a signal output terminal; first and second n-channel field effect transistors of the enhancement mode type and first and second p-channel field effect transistors of the enhancement mode type, each of said field effect transistors having source and drain and gate electrodes, the source electrodes of said first n-channel transistor and of said first p-channel transistor being respectively connected to said first terminal and to said second terminal, the drain electrodes of said first n-channel transistor and of said first p-channel transistor being respectively connected to the source electrode of said second n-channel transistor and to the source electrode of said second p-channel transistor, the drain electrodes of said second n-channel transistor and of said second p-channel transistor being connected to said output terminal; low-pass filtering network means having an input connection to which said output terminal connects and having first and second output connections for providing first and second direct bias potentials each equal to the quiescent potential at said output terminal, said second output connection connected to the gate electrodes of said second n-channel and second p-channel transistors to apply said second direct bias potential to each of them; means for additively combining said input signal potential with said first direct bias potential to provide a potential to the gate electrodes of said first n-channel and first p-channel transistors.

Claim 19

A cascode configuration comprising: means for supplying an input signal potential; first and second terminals for receiving an operating voltage therebetween; a signal output terminal; first and second n-channel field effect transistors of the enhancement mode type and first and second p-channel field effect transistors of the enhancement mode type, each of said field effect transistors having source and drain and gate electrodes, the source electrodes of said first n-channel transistor and of said first p-channel transistor being respectively connected to said first terminal and to said second terminal, the drain electrodes of said first n-channel transistor and of said first p-channel transistor being respectively connected to the source electrode of said second n-channel transistor and to the source electrode of said second p-channel transistor, the drain electrodes of said second n-channel transistor and of said second p-channel transistor being connected to said output terminal; low-pass filtering network means having an input connection to which said output terminal connects and having first and second output connections for providing first and second direct bias potentials each equal to the quiescent potential at said output terminal, said second output connection connected to the gate electrodes of said second n-channel and second p-channel transistors to apply said second direct bias potential to each of them; means for additively combining said input signal potential with said first direct bias potential to provide a potential to the gate electrodes of said first n-channel and first p-channel transistors.

Claim 20

A cascode onfiguration as set forth in claim 15 wherein said low pass filtering network means includes first and second resistances respectively connecting said output terminal to a point of connection and to an interconnection between the gate electrodes of said second n-channel and second p-channel transistors, a first capacitor connected for by-passing said point of interconnection for signal, and a second capacitor connected for by-passing said interconnection between the gate electrodes of said second n-channel and said second p-channel transistors for signal; and wherein said means for additively combining said input signal with said first direct bias potential includes a coil connecting said point of connection to an interconnection between the gate electrodes of said first n-channel and said first p-channel transistors and means for inducing input signal potential across said coil.

Claim 21

A cascode configuration as set forth in claim 16 wherein said coil is the secondary winding of a transformer also having a primary winding, included in said means for inducing input signal potential.