Electronic timepiece

Claim 2

An electronic timepiece comprising: a frequency standard; a frequency divider which divides an output frequency of said frequency standard to provide output pulse signals; a time counter driven by said output pulse signals to provide time information signals; counter means coupled to said time counter to form a serial counter chain and operative to function in one of first and second modes; circuit means connected between said time counter and said counter means for permitting transfer of said time information signals to said counter means whereby said counter means operates in said first mode for producing a first data signal, said circuit means including means for interrupting the transfer of said time information signals to said counter means and permitting entry of input signals other than said time information signals into said counter means whereby said counter means operates in said second mode for producing a second data signal other than said first data signal; means for producing said input signals; means for controlling said circuit means to cause said counter means to operate in one of said first and second modes; and means for providing a display of said time information signals, first data signal and said second data signal.

Claim 3

An electronic timepiece according to claim 1, in which said control means comprises a control terminal by which said one of first and second modes is fixedly set.

Claim 4

An electronic timepiece according to claim 1, in which said counter means constitutes part of said time counter.

Claim 5

An electronic timepiece according to claim 3, in which said counter means comprises a days counter and a months counter, and in which said first data signal is a calendar data signal and said second data signal is an alarm data signal.

Claim 6

An electronic timepiece comprising: a frequency standard; a frequency divider which divides an output frequency of the frequency standard to provide output pulse signals; a time counter driven by said output pulse signals to provide time information signals in response thereto; counter means operative to function in first and second modes; change-over circuit means including first means for interconnecting said counter means with said time counter to pass said time information signals to said counter means by which said counter means operates in said first mode for producing a first data signal, and second means for inhibiting said first means to interrupt said counter means from said time counter, said second means including means for permitting the setting-in of input signals other than said time information signals into said counter means by which said counter means operates in said second mode for storing a second data signal other than said first data signal; means for producing said input signals; means for controlling said change-over circuit means to set said counter means in one of said first and second means; and display means for providing a display of said time information signals, said first data signal and said second data signal.

Claim 7

An electronic timepiece comprising: a frequency standard; a frequency divider which divides an output frequency of the frequency standard to provide output pulse signals; a time counter driven by said output pulse signals to provide time information signals in response thereto; counter means operative to function in first and second modes; change-over circuit means including first means for interconnecting said counter means with said time counter to pass said time information signals to said counter means by which said counter means operates in said first mode for producing a first data signal, and second means for inhibiting said first means to interrupt said counter means from said time counter, said second means including means for permitting the setting-in of input signals other than said time information signals into said counter means by which said counter means operates in said second mode for storing a second data signal other than said first data signal; means for producing said input signals; means for controlling said change-over circuit means to set said counter means in one of said first and second means; and display means for providing a display of said time information signals, said first data signal and said second data signal.

Claim 8

An electronic timepiece comprising: a frequency standard; a frequency divider which divides an output frequency of the frequency standard to provide output pulse signals; a time counter driven by said output pulse signals to provide time information signals in response thereto; counter means operative to function in first and second modes; change-over circuit means including first means for interconnecting said counter means with said time counter to pass said time information signals to said counter means by which said counter means operates in said first mode for producing a calendar information signal, and second means for inhibiting said first means to interrupt said counter means from said time counter, said second means including means for permitting the setting-in of input signals other than said time information signals into said counter means by which said counter means operates in said second mode for storing data other than said calendar information signal; means for producing said input signals; means for controlling said change-over circuit means to set said counter means in one of said first and second modes; and display means for providing a display of said time information signals, said calendar information signal and said data.

Claim 9

An electronic timepiece comprising: a frequency standard; a frequency divider which divides an output frequency of the frequency standard to provide output pulse signals; a time counter driven by said output pulse signals to provide time information signals in response thereto; counter means operative to function in first and second modes; change-over circuit means including first means for interconnecting said counter means with said time counter to pass said time information signals to said counter means by which said counter means operates in said first mode for producing a calendar information signal, and second means for inhibiting said first means to interrupt said counter means from said time counter, said second means including means for permitting the setting-in of input signals other than said time information signals into said counter means by which said counter means operates in said second mode for storing data other than said calendar information signal; means for producing said input signals; means for controlling said change-over circuit means to set said counter means in one of said first and second modes; and display means for providing a display of said time information signals, said calendar information signal and said data.

Claim 10

An electronic timepiece according to claim 6, in which said counter means comprises a days counter, a first flip-flop coupled to an output of said days counter, a months counter, and a second flip-flop coupled to an output of said months counter.

Claim 11

An electronic timepiece according to claim 7, in which said days counter and said months counter serve as a minutes memory counter and an hours memory counter, respectively, by which alarm time data can be stored.

Claim 12

An electronic timepiece according to claim 8, further comprising a coincidence detection circuit connected to said time counter and said counter means for producing a coincidence signal when said time information signals coincide with said alarm time data, and means for indicating said alarm time data in response to said coincidence signal.

Claim 13

In an electronic timepiece having a frequency standard, a frequency divider which divides an output frequency of the frequency standard to provide output pulse signals, a time counter driven by said output pulse signals from said frequency divider, and display means for displaying the contents of said time counter, the improvement comprising: counter means composed of a days counter and a months counter coupled to said time counter in series to form a serial counter chain and receiving an output signal from said time counter to perform a calendar function and an alarm function; and change-over means disposed in said counter chain between said time counter and said counter means, said change-over means selectively changing over the functions of said counter means; said counter means including flip-flops which are coupled to outputs of said days counter and said months counter, respectively, by said change-over means whereby said days counter and said months counter may function as a minutes memory counter and an hours memory counter, respectively, in said alarm function.

Claim 14

In an electronic timepiece having a frequency standard, a frequency divider which divides an output frequency of the frequency standard to provide output pulse signals, a time counter driven by said output pulse signals from said frequency divider, and display means for displaying the contents of said time counter, the improvement comprising: counter means composed of a days counter and a months counter coupled to said time counter in series to form a serial counter chain and receiving an output signal from said time counter to perform a calendar function and an alarm function; and change-over means disposed in said counter chain between said time counter and said counter means, said change-over means selectively changing over the functions of said counter means; said counter means including flip-flops which are coupled to outputs of said days counter and said months counter, respectively, by said change-over means whereby said days counter and said months counter may function as a minutes memory counter and an hours memory counter, respectively, in said alarm function.

Claim 15

The improvement according to claim 10, in which said counter means is connected to said display means whereby the contents of said counter means can be displayed by said display means.

Claim 16

The improvement according to claim 10, in which said change-over means includes a carry inhibiting gate which can be actuated to inhibit the passage of said output signals from said time counter to said counter means.

Claim 17

The improvement according to claim 10, in which said display means comprises a current time display station to which said time counter is coupled, and a function display station to which said counter means is coupled, whereby the contents of said memory counters can be displayed by said function display station.

Claim 18

The improvement according to claim 10, further comprising a coincidence detecting circuit coupled to said time counter and said memory counters and generating a coincidence signal when a current time stored in said time counter comes into coincidence with an alarm time stored in said memory counters, and alarm means responsive to said coincidence signal to produce an alarm warning therefrom.

Claim 19

The improvement according to claim 14, in which said alarm means includes an alarm circuit connected to said detecting circuit to provide an alarm actuating signal in response to said coincidence signal, and an audible alarm unit responsive to said alarm actuating signal for thereby providing an audible alarm signal.

Claim 20

The improvement according to claim 15, in which said alarm means further includes means for inhibiting the passage of said alarm coincidence signal to said alarm circuit, thereby stopping the operation of said audible alarm unit.

Claim 21

The improvement according to claim 10, further comprising an automatic month-end correction device connected to said counter means for automatically resetting the contents of said counter means to correspond with the first day of the following month immediately after the end of each calendar month.

Claim 22

The improvement according to claim 17, in which said month-end correction device comprises a month-end detection circuit connected to said days counter to detect contents of said days counter which correspond to the ends of months and to generate output signals indicative thereof, a months detection circuit connected to said months counter to detect odd-numbered months, even-numbered months and February and generate output signals indicative thereof, a month-end correction signal gate connected to said days counter and said months counter and responsive to the output signals from said month-end detection circuit and said months detection circuit from generating an automatic correction signal by which said days counter is reset to a count of one corresponding to a first day of the following month and said months counter is advanced by a count of one.

Claim 23

The improvement according to claim 18, further comprising digit selector switch means, correction switch means, a shift register coupled to said digit selector switch means and generating at least a days correction designating signal and a months correction designating signal when said digit selector switch means is actuated, means for generating correction pulses when said correction switch means is actuated, a first correction selecting gate circuit connected between said change-over means and said days counter and responsive to said days correction designating signal and said correction pulses for correcting said days counter, and a second correction selecting gate circuit connected between said days counter and said months counter and responsive to said months correction designating signal and said correction pulses for correcting said months counter.

Claim 24

The improvement according to claim 19, in which said change-over means and said month-end correction signal gate are rendered inoperative in the alarm function, and in which said first and second correction selecting gate circuits serve as means for writing in the minutes and hours of alarm time data in said minutes memory counter and said hours memory counter, respectively, in response to said correction pulses in the alarm function.

Claim 25

The improvement according to claim 10, further comprising a reset control terminal coupled to said time counter and said counter means, and in which the application of a reset signal to said reset control terminal causes the contents of said time counter and said counter means to be brought into coincidence with each other.

Claim 26

The improvement according to claim 21, in which said time counter comprises a minutes counter and an hours counter, each of said minutes counter and said hours counter comprising a series of flip-flops arranged to perform a counting function, and automatic reset means coupled to said minutes counter and said hours counter.

Claim 27

The improvement according to claim 22, in which said automatic reset means comprises count detection means for detecting a maximum count value in said minutes counter and said hours counter, and latch circuit means including a set terminal coupled to receive an output signal from said count detection means and a reset terminal coupled to receive electric pulses at a constant frequency, whereby said latch circuit means is set by an output signal from said count detection means when said maximum count value is exceeded thereby causing a reset signal to be generated by said latch circuit means, said reset signal causing said minutes counter and said hours counter to be reset to the count of zero.

Claim 28

The improvement according to claim 22, in which said counter means comprises a days counter and a months counter, each of said days counter and said months counter comprising a series of flip-flops arranged to perform a counting function, and automatic reset means coupled to said days counter and said months counter.

Claim 29

The improvement according to claim 24, in which said automatic reset means comprises count detection means for detecting a maximum count value in said days counter and said months counter, and latch circuit means including a set terminal coupled to receive an output signal from said count detection means and a reset terminal coupled to receive electric pulses at a constant frequency.

Claim 30

The improvement according to claim 25, in which a first stage of each series of flip-flops of said minutes counter and said days counter has a set terminal coupled to said reset control terminal and remaining stages of said each series of flip-flops have reset terminals coupled to said reset control terminal, whereby when a reset signal is applied to said reset control terminal said first stage of said each series of flip-flops is set to a count value of one and said remaining stages of said each series of flip-flops are reset to a count value of zero.

Claim 31

The improvement according to claim 10, in which said days counter comprises a divide-by ten counter and a divide-by four counter and said months counter comprises a divide-by twelve counter.

Claim 32

The improvement according to claim 27, in which said flip-flops are coupled to said divide-by four counter and said divide-by twelve counter by the action of said change-over means in said alarm function, whereby said days counter and said months counter are converted into said minutes memory counter and said hours memory counter in said alarm function.

Claim 33

The improvement according to claim 28, in which said counter means further comprises a control terminal coupled to said days counter and said months counter, whereby said days counter and said months counter serve to provide said calendar function in response to a control voltage applied to said control terminal.

Claim 34

The improvement according to claim 29, further comprising an automatic month-end correction device connected to said counter means for automatically resetting the contents of said counter means to correspond with the first day of the following month immediately after the end of each calendar month.

Claim 35

The improvement according to claim 30, in which said month-end correction device comprises a month-end detection circuit connected to said days counter to detect contents of said days counter which correspond to the ends of months and to generate output signals indicative thereof, a months detection circuit connected to said months counter to detect odd-numbered months, even-numbered months and February and generate output signals indicative thereof, a month-end correction signal gate connected to said days counter and said months counter and responsive to the output signals form said month-end detection circuit and said months detection circuit for generating an automatic correction signal by which said days counter is reset to a count of one corresponding to a first day of the following month and said months counter is advanced by a count of one.

Claim 36

The improvement according to claim 31, in which said counter means further comprises means for setting the date to a 29th of February during time setting.

Claim 37

The improvement according to claim 32, in which said counter means further comprises means for halting counting operations of said days counter and said months counter after the date has been set to the 29th of February.

Claim 38

The improvement according to claim 31, in which said month-end detection circuit detects count values corresponding to the 32nd day or more of the odd-numbered months, the 31st day or more of the even-numbered months and the 30th day or more of February, whereby the date is immediately set to the 1st day of the following month, with counting continuing thereafter.

Claim 39

The improvement according to claim 31, in which the contents of said divide-by ten counter of said days counter is automatically reset to a count of value of zero or one when the contents of said divide-by ten counter reaches a value of eleven or more.

Claim 40

The improvement according to claim 31, in which said months detection circuit comprises an AND-OR gate for detecting the even-numbered months.

Claim 41

The improvement according to claim 29, in which when said control terminal is applied with a control voltage such that said memory counters are provided, alarm time can be set whereas counting of days and months is discontinued.

Claim 42

The improvement according to claim 29, in which when said control terminal is applied with said control voltage such that said days and months counters are provided, the contents of said days counter are unaffected when correction is performed of the contents of said months counter and a month-end correction is performed when the contents of the days counter are corrected, said month-end correction being in conformity with the contents of said months counter.

Claim 43

The improvement according to claim 38, in which means are provided such that the contents of said months counter are unaffected when the contents of said days counter are corrected.

Claim 44

The improvement according to claim 29, in which the count of said days and months counters advances from 1 to 31 and from 1 to 12, respectively, and the count of the hours and minutes counters of said alarm memory counters advances from 0 to 59 and from 0 to 11, respectively.

Claim 45

The improvement according to claim 29, in which means are provided such that the divide-by-4 and divide-by-10 counters of said days counters are operable to begin counting at different times with respect to a standard clock signal.

Claim 46

The improvement according to claim 41, in which a first counter stage of said days counter and a first counter stage of said months counter each comprises an edge-triggered type flip-flop, and invertor means coupled to the input terminals of said first counter stages, whereby said first counter stages of said days counter and said months counter are caused to change state at their respective outputs in response to mutually opposite directions of change of input signal voltage, said input signal being applied to said invertor means.

Claim 47

The improvement according to claim 15, in which said alarm circuit comprises a transistor and a current-limiting resistor connected in series with respect to a power supply.

Claim 48

The improvement according to claim 43, in which said current-limiting resistor is coupled to an emitter of said transistor whose base electrode is coupled to receive said alarm actuating signal.