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Patent US4088903A successfully refreshed from Google Patents.
US4088903A
Expired / Lapsed
US
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Bistable circuits
Assignee: BAE Systems Electronics Ltd
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Filing: 1977-02-14
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Granted: 1978-05-09
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Expires: 1997-02-14
Abstract
Abstract A bistable of the emitter coupled type is provided in which the two halves of the bistable are effectively made independently bistable by providing feedback cross-coupling via an additional pair of emitter coupled transistors. This together with the buffering of the outputs which are taken from the additional transistors reduces the effects of clock breakthrough and the effective capacitance of the output modes and provides for a significant increase in potential working speed.
Inventors
- 👤 Edwin V. Jones
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:48
CPC Classifications
H; H03; H03L; H03L1/00; H03L1/02; G; G04; G04G; G04G3/00; G04G3/02; H03K; H03K3/00; H03K3/01; H03K3/011; H03K3/012; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/288; H03K3/2885; H03K3/353; H03K3/356; H03K3/356017; H03K3/356034; H03K3/356043; H10; H10D; H10D89/00; H10D89/10; H10P; H10P95/00
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
209 words
A bistable including first and second pairs of transistors the transistors within a pair having their collectors connected by a current path and arranged to share a current; a third pair of transistors having their emitters connected by a current path and collectors arranged to share a current; first transistors of the first and second pairs respectively having emitters connected by a current path; second transistors of the first and second pairs respectively having emitters connected by a current path; means for applying data signals to a first transistor of the first and second pairs; means for applying clock signals to switch current from a second to a first transistor of the first and second pairs in dependence upon the state of the data signals and feedback paths between the collectors of the first pair and the base of a first transistor of the third pair; between the collector of the first transistor of the third pair and the base of the second transistor of the first pair; between the collectors of the second pair and the base of the second transistor of the third pair and between the collector of the second transistor of the third pair and the base of the second transistor of the second pair.
Claim 2
Dependent Claim
209 words
A bistable including first and second pairs of transistors the transistors within a pair having their collectors connected by a current path and arranged to share a current; a third pair of transistors having their emitters connected by a current path and collectors arranged to share a current; first transistors of the first and second pairs respectively having emitters connected by a current path; second transistors of the first and second pairs respectively having emitters connected by a current path; means for applying data signals to a first transistor of the first and second pairs; means for applying clock signals to switch current from a second to a first transistor of the first and second pairs in dependence upon the state of the data signals and feedback paths between the collectors of the first pair and the base of a first transistor of the third pair; between the collector of the first transistor of the third pair and the base of the second transistor of the first pair; between the collectors of the second pair and the base of the second transistor of the third pair and between the collector of the second transistor of the third pair and the base of the second transistor of the second pair.
Claim 3
Dependent Claim
41 words
A bistable as claimed in claim 1 in which data signals are applied in operation to each first transistor of the first and second pairs, the signals applied to one first transistor being the complement of those applied to the other.
Claim 4
Dependent Claim
76 words
A bistable as claimed in claim 1 in which the means for applying clock signals comprises a fourth pair of transistors having emitters connected by a current path to share a current, the collectors of the transistors being respectively connected to the current paths between the emitters of the first and second transistors of the first and second pairs and clock signals are applied in operation to a base of a transistor of the fourth pair.
Claim 5
Dependent Claim
40 words
A bistable as claimed in claim 3 in which clock signals are applied in operation to the base of each transistor of the fourth pair the signals applied to one transistor being the complement of those applied to the other.
References Cited (Backward Citations)
US3042814A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-05-08 | 1981-11-07 | 1982-05-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-05-08 | 1985-11-07 | 1986-05-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-05-08 | 1989-11-07 | 1990-05-09 | $7700.00 | Window Closed / Lapsed |