Patent US4987394A successfully refreshed from Google Patents.
Patent US4088029A successfully refreshed from Google Patents.
← Back to Patent Explorer
US4088029A Expired / Lapsed US ⏱️ 0.0 years remaining

Ultrasonic flaw detector

Assignee: Tokyo Keiki Inc
•
Filing: 1976-03-22
•
Granted: 1978-05-09
•
Expires: 1996-03-22
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract An ultrasonic flaw detector having a probe for transmitting and receiving an ultrasonic wave, a receiver for producing an electric signal in response to the ultrasonic signal from the probe, a plurality of gates and a counter having a corresponding number of independent display elements for indication of detected results. In this case, the detected result can be indicated without using a cathode ray tube.

Inventors

  • 👤 Eiji Yamamoto
  • 👤 Koji Ohta

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 07:25
CPC Classifications
G; G01; G01N; G01N29/00; G01N29/36; G01N29/38; Y; Y10; Y10S; Y10S73/00; Y10S73/901

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 321 words
An ultrasonic flaw detector comprising: (a) means including a signal generator for applying a transmitting pulse to a probe, said probe transmitting an ultrasonic wave to an object having a flaw to be detected; (b) receiver means for receiving a reflected ultrasonic wave arriving at said probe from a flaw in the object being detected due to reflection of said transmitting ultrasonic wave from said flaw; (c) gate circuit means including a gate signal generator which produces plural output signals, said plural output signals occurring without a gap from a preceding one of said signals, AND circuits, peak hold circuits and analog-digital converters, each of said AND circuits receiving the output signal from said gate signal generator sequentially, and an output signal from each of said AND circuits being supplied through each of said peak hold circuits to each of said analog-digital converters; (d) means for coupling an output from said receiver means to said gate circuit means; (e) clock pulse generating means for producing a clock pulse; (f) preset means for receiving the clock pulse from said clock pulse generating means and said transmitting pulse from said signal generator and producing an output signal for a fixed count of clock pulses from said clock pulse generating means; (g) delay circuit means coupled to an output of said preset means and producing a single output signal for each cycle of said signal generator, said single output signal being applied to said gate circuit means, said plural output signals from said gate signal generator being produced in response to said single output signal from said delay circuit means; and (h) counter indication means including latch circuits and display elements, each of said display elements receiving an output signal from each of said analog-digital converters through each of said latch circuits to give quantitative data concerning a flaw magnitude in said object being detected in response to measurements of said reflected ultrasonic wave.
Claim 2
Dependent Claim 321 words
An ultrasonic flaw detector comprising: (a) means including a signal generator for applying a transmitting pulse to a probe, said probe transmitting an ultrasonic wave to an object having a flaw to be detected; (b) receiver means for receiving a reflected ultrasonic wave arriving at said probe from a flaw in the object being detected due to reflection of said transmitting ultrasonic wave from said flaw; (c) gate circuit means including a gate signal generator which produces plural output signals, said plural output signals occurring without a gap from a preceding one of said signals, AND circuits, peak hold circuits and analog-digital converters, each of said AND circuits receiving the output signal from said gate signal generator sequentially, and an output signal from each of said AND circuits being supplied through each of said peak hold circuits to each of said analog-digital converters; (d) means for coupling an output from said receiver means to said gate circuit means; (e) clock pulse generating means for producing a clock pulse; (f) preset means for receiving the clock pulse from said clock pulse generating means and said transmitting pulse from said signal generator and producing an output signal for a fixed count of clock pulses from said clock pulse generating means; (g) delay circuit means coupled to an output of said preset means and producing a single output signal for each cycle of said signal generator, said single output signal being applied to said gate circuit means, said plural output signals from said gate signal generator being produced in response to said single output signal from said delay circuit means; and (h) counter indication means including latch circuits and display elements, each of said display elements receiving an output signal from each of said analog-digital converters through each of said latch circuits to give quantitative data concerning a flaw magnitude in said object being detected in response to measurements of said reflected ultrasonic wave.
Claim 3
Dependent Claim 70 words
An ultrasonic flaw detector as claimed in claim 1 in which said gate circuit means includes a plurality of gate circuits and the same number of analog to digital converters and said counter indication means includes a plurality of independent indication elements, the output from each of said analog to digital converters being applied to a corresponding indication element to numerically indicate the magnitude and position of the detected flaw.
Claim 4
Dependent Claim 27 words
An ultrasonic flaw detector as claimed in claim 1 in which a common analog to digital converter is inserted between said receiver and said gate circuit means.
Claim 5
Dependent Claim 48 words
An ultrasonic flaw detector as claimed in claim 1 in which the signal generator is coupled to said preset member for controlling the same, reset means coupled to the counter indication means, said signal generator being also coupled to said reset means for time-controlling the counter indication means.

References Cited (Backward Citations)

US3041872A Cited
US3260105A Cited
US3287963A Cited
US3416364A Cited
US3485087A Cited
US3482435A Cited
US3688565A Cited
US3805597A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1981-05-08 1981-11-07 1982-05-09 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1985-05-08 1985-11-07 1986-05-09 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1989-05-08 1989-11-07 1990-05-09 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag