US4087852A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Microprocessor for an automatic word-processing system
Assignee: Xerox Corp
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Filing: 1974-01-02
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Granted: 1978-05-02
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Expires: 1994-01-02
Abstract
Abstract The keyboard, printer and recording means are peripheral units under the control of a microprocessor including a programmable read-only memory from which appropriate control instructions are derived. Control signal sequences for operating the word processing system are the result of addressing of the read-only memory in accordance with the sensed status of the attached peripheral units and a priority schedule. The peripheral units operate semiautomatically in response to control instructions to execute a commanded function. Control instructions fall into various classes for controlling peripherals, determining the status of peripherals or performing internal operations within the microprocessor. The format of the next address or sequence of addresses to be applied to the read-only memory is dependent on the class of the prior control instruction or the response of a peripheral unit to a particular control signal.
Inventors
- 👤 Kenneth C. Campbell
- 👤 Werner Schaer
- 👤 Harry W. Swanstrom
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 11:32
CPC Classifications
B; B41; B41J; B41J5/00; B41J5/30; B41J5/31; B41J5/40; B41J5/42
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
288 words
A microprocessor which communicates with a plurality of peripheral devices via a data bus and an instruction word bus, said microprocessor having a read-only-memory (hereinafter abbreviated ROM) which generates a plurality of instruction words on said instruction word bus in response to a corresponding ROM address, said microprocessor including an arithmetic logic unit (hereinafter abbreviated ALU) for performing arithmetic and logic functions, said microprocessor further including a plurality of addressable general purpose data storage registers, each of said instruction words being applied in parallel to said peripheral devices, said ROM, said ALU and said general purpose registers, said combination comprising: means for addressing said peripheral devices, means within each of said peripheral devices which is responsive to said means for addressing and is further responsive to instruction words transmitted over said instruction word bus to effect a predetermined operation when a control command is specified by said instruction words and to provide a status condition when a status check command is specified by said instruction words, means responsive to said status condition to specify a predetermined succeeding ROM address to be applied to said ROM, means within said ALU and said general purpose data storage registers responsive to instruction words to effect a predetermined data processing operation on data transmitted over said data bus from said peripheral devices when a data processing command is specified by said instruction words and to provide a test condition result when a test data command is specified by said instruction words, means responsive to said instruction words for determining which general purpose register will have its contents processed by said ALU and means responsive to said test condition result to specify a predetermined succeeding ROM address to be applied to said ROM.
Claim 2
Dependent Claim
288 words
A microprocessor which communicates with a plurality of peripheral devices via a data bus and an instruction word bus, said microprocessor having a read-only-memory (hereinafter abbreviated ROM) which generates a plurality of instruction words on said instruction word bus in response to a corresponding ROM address, said microprocessor including an arithmetic logic unit (hereinafter abbreviated ALU) for performing arithmetic and logic functions, said microprocessor further including a plurality of addressable general purpose data storage registers, each of said instruction words being applied in parallel to said peripheral devices, said ROM, said ALU and said general purpose registers, said combination comprising: means for addressing said peripheral devices, means within each of said peripheral devices which is responsive to said means for addressing and is further responsive to instruction words transmitted over said instruction word bus to effect a predetermined operation when a control command is specified by said instruction words and to provide a status condition when a status check command is specified by said instruction words, means responsive to said status condition to specify a predetermined succeeding ROM address to be applied to said ROM, means within said ALU and said general purpose data storage registers responsive to instruction words to effect a predetermined data processing operation on data transmitted over said data bus from said peripheral devices when a data processing command is specified by said instruction words and to provide a test condition result when a test data command is specified by said instruction words, means responsive to said instruction words for determining which general purpose register will have its contents processed by said ALU and means responsive to said test condition result to specify a predetermined succeeding ROM address to be applied to said ROM.
Claim 3
Dependent Claim
31 words
A microprocessor as defined in claim 1 further including means responsive to instruction words to test for the presence of blank characters in data in said general purpose data storage registers.
Claim 4
Dependent Claim
60 words
A microprocessor as defined in claim 1 further including means responsive to instruction words to effect a predetermined comparison between characters permanently stored within said ROM and data characters received for said peripheral devices, and means responsive to results of said comparison to effect a predetermined processing (arithmetic or logic) function upon said data characters received from said peripheral devices.
Claim 5
Dependent Claim
30 words
A microprocessor as defined in claim 3 further including means responsive to instruction word to test for the presence of blank characters in data in said general purpose data registers.
Claim 6
Dependent Claim
34 words
A microprocessor as defined in claim 1 further including means within each of said peripheral devices which is responsive to instruction words to effect an idle or no operation condition of said peripheral devices.
Claim 7
Dependent Claim
44 words
A microprocessor as defined in claim 1 further including means within said ALU, said general purpose data storage registers and said peripheral devices, responsive to instruction words to receive data from an external source and to effect a predetermined operation upon said external data.
Claim 8
Dependent Claim
34 words
A microprocessor as defined in claim 6 further including means within each of said peripheral devices which is responsive to instruction words to effect an idle or no operation condition of said peripheral devices.
Claim 9
Dependent Claim
31 words
A microprocessor as defined in claim 7 further including means responsive to instruction words to test for the presence of blank characters in data in said general purpose data storage registers.
Claim 10
Dependent Claim
60 words
A microprocessor as defined in claim 8 further including means responsive to instruction words to effect a predetermined comparison between characters permanently stored within said ROM and data characters received from said peripheral devices, and means responsive to results of said comparison to effect a predetermined processing (arithmetic or logic) function upon said data characters received from said peripheral devices.
Claim 11
Dependent Claim
77 words
A microprocessor as defined in claim 1 further including means within said ALU and said general purople data storage registers responsive to instruction words to effect a predetermined logical functional operation or an arithmetic function operation on data from said peripheral devices, means within said ALU responsive to said instruction words for performing a carry operation in said arithmetic function operation, and means responsive to said instruction words to prevent data from being transferred from said ROM.
Claim 12
Dependent Claim
39 words
A microprocessor as defined in claim 1 further including means within each of said peripheral devices responsive to instruction words to provide a status condition on a particular one of a plurality of peripheral status conditions to be tested.
Claim 13
Dependent Claim
77 words
A microprocessor as defined in claim 11 further including means within said ALU and said general purpose data storage registers responsive to instruction words to effect a predetermined logical functional operation or an arithmetic function operation on data from said peripheral devices, means within said ALU responsive to said instruction words for performing a carry operation in said arithmetic function operation, and means responsive to said instruction words to prevent data from being transferred from said ROM.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-05-01 | 1981-10-31 | 1982-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-05-01 | 1985-10-31 | 1986-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-05-01 | 1989-10-31 | 1990-05-02 | $7700.00 | Window Closed / Lapsed |