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Patent US4087850A successfully refreshed from Google Patents.
US4087850A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Power supply circuit
Assignee: Sony Corp
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Filing: 1977-01-21
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Granted: 1978-05-02
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Expires: 1997-01-21
Abstract
Abstract In a power supply circuit having a circuit for supplying an input DC voltage through a switching element to a winding, a circuit for producing a desired DC voltage by switching the switching element with a pulse and a circuit for detecting the level of the DC output voltage, and changing the duty ratio of the pulse with the detected output so as to stabilize the DC output voltage at a constant value. There is provided a circuit which limits the maximum value of the duty ratio of the pulse.
Inventors
- 👤 Akio Koizumi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 15:05
CPC Classifications
H; H02; H02M; H02M3/00; H02M3/22; H02M3/24; H02M3/28; H02M3/325; H02M3/335; H02M3/33507
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
194 words
A power supply circuit comprising: (a) an input DC voltage source; (b) a winding connected to said DC voltage source; (c) a switching means connected to said winding; (d) means for producing an AC voltage in response to the switching function of said switching means; (e) means for converting said AC voltage to an output DC voltage; (f) means for detecting said output DC voltage and for producing a detected DC output signal in response to said output DC voltage; (g) an oscillator for generating pulse signals; (h) a modulator supplied with said pulse signals and said detected DC output signal and for producing pulse width modulated signals in response to said detected DC output signal; (i) means for supplying said pulse width modulated signals to said switching means; and (j) means for limiting a maximum value of the duty ratio of said pulse width modulated signal, said limiting means including means for frequency-dividing said pulse signals from said oscillator and an AND-gate circuit which is supplied with an output signal from said frequency-dividing means and with the pulse width modulated signal from said modulator, for supplying an AND-gate output to said supplying means.
Claim 2
Dependent Claim
194 words
A power supply circuit comprising: (a) an input DC voltage source; (b) a winding connected to said DC voltage source; (c) a switching means connected to said winding; (d) means for producing an AC voltage in response to the switching function of said switching means; (e) means for converting said AC voltage to an output DC voltage; (f) means for detecting said output DC voltage and for producing a detected DC output signal in response to said output DC voltage; (g) an oscillator for generating pulse signals; (h) a modulator supplied with said pulse signals and said detected DC output signal and for producing pulse width modulated signals in response to said detected DC output signal; (i) means for supplying said pulse width modulated signals to said switching means; and (j) means for limiting a maximum value of the duty ratio of said pulse width modulated signal, said limiting means including means for frequency-dividing said pulse signals from said oscillator and an AND-gate circuit which is supplied with an output signal from said frequency-dividing means and with the pulse width modulated signal from said modulator, for supplying an AND-gate output to said supplying means.
Claim 3
Dependent Claim
72 words
A power supply circuit according to claim 1 further including a second DC voltage detecting means which detects the voltage of said input DC voltage source and produces a second DC voltage output signal and a second AND-gate circuit supplied with said second DC voltage output signal and the output signal from said frequency-dividing means, an output from said second AND-gate circuit being supplied to said modulator and first-mentioned AND-gate circuit, respectively.
Claim 4
Dependent Claim
48 words
A power supply circuit as claimed in claim 2, wherein said frequency-dividing means includes first and second flip-flop circuits connected in series, an OR-gate circuit supplied with output signals from said first and second flip-flop circuits, and means for connecting said OR-gate circuit to said second AND-gate circuits.
Claim 5
Dependent Claim
47 words
A power supply circuit according to claim 3 further including a third AND-gate circuit supplied with an output signal from said second flip-flop circuit and said second DC voltage output signal, and a second OR-gate circuit supplied with output signals from said second and third AND-gate circuits.
Claim 6
Dependent Claim
62 words
A power supply circuit according to claim 4 further including a fourth AND-gate circuit supplied with output signals from said first and second flip-flop circuits, a fifth AND-gate circuit supplied with an output signal from said fourth AND-gate circuit and said second DC voltage signal and means for supplying an output signal from said fifth AND-gate circuit to said second OR-gate circuit.
References Cited (Backward Citations)
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-05-01 | 1981-10-31 | 1982-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-05-01 | 1985-10-31 | 1986-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-05-01 | 1989-10-31 | 1990-05-02 | $7700.00 | Window Closed / Lapsed |