Asynchronous to synchronous converter

Claim 1

In a clock pulse generator for producing clock pulses in synchronism with data bits of non-return-to-zero code being transmitted at a variable data rate as a stream of high and low level data pulses each of which represents one or more bits, each data word including a prefix having at least one pulse representing a predetermined number of bits, said generator comprising a master clock, a bit clock system including a first and a second bit clock generator, said first bit clock generator being connected with a source of data pulses and with the master clock for producing a first timing signal when the data pulse has a duration which corresponds to one bit time of a data pulse, said second bit clock generator being connected with the master clock and with the output of the first bit clock generator for producing succeeding timing signals when said data pulse has a duration which exceeds the bit time of a data pulse, and measurement means connected with said source of data pulses for measuring the time duration of the prefix pulses to produce a measurement signal having a value corresponding to the bit time at the existing data rate, and clock signal generating means connected with the first and second bit clock generators and responsive to said timing signals for producing a serial stream of clock pulses in synchronism with the bits of said data pulses, the improvement wherein said first bit clock generator comprises first multiplexing means having first and second inputs, an output and a selector input for selectively connecting the first or second input with said output, said first input being connected with said measurement means for receiving a signal corresponding to one-half bit time of a high level data pulse, said second input being connected with said measurement means for receiving a signal corresponding to one-half bit time of a low level data pulse, first comparator means having first and second inputs adapted to receive signals for value comparison and having an output adapted to produce said first timing signal when the signal applied to said second input exceeds the signal applied to said first input of the first comparator means, the output of said first multiplexing means being connected with said first input of said first comparator means, said selector input of the first multiplexing means being connected with said source of data pulses, and first counting means having an input connected with said master clock and having an output connected with said second input of said first comparator means, and means for starting said first counting means at the initiation of a data pulse whereby said first timing signal is produced one-half bit time after initiation of a high level data pulse or one-half bit time after initiation of a low level data pulse.