US4087640A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Data input control system
Assignee: Toshiba Corp
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Filing: 1976-08-17
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Granted: 1978-05-02
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Expires: 1996-08-17
Abstract
Abstract A data input control system which provides a processor with control data including micro-instructions from a control storage on a time-division basis. The processor and the control storage are respectively integrated on one-chip semiconductor devices. The data input control system is effective for reducing the number of necessary terminals on the one-chip semiconductor device for the processor.
Inventors
- 👤 Kazuyuki Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 00:50
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7835; G06F13/00; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
198 words
A data input control system for reducing the number of terminals required by a processor without reducing the functionality of said processor comprising: a control storage means for storing control data integrated on a one-chip semiconductor device, a processor means integrated on another one-chip semiconductor device having input terminals for receiving said control data, means for generating a clock pulse, gating means for supplying said control data read out from said control storage to said processor means in response to said clock pulse, means for controlling said gating means on a time-division basis satisfying the following relationships ##EQU1## wherein A is the access time of said control storage; B is the memory cycle time of said control storage; C is the number of control data input terminals of said processor; D is the bit length of said control data; n is the number of division times of said control data in said memory cycle time B; and, T is the period of said clock pulse; means for storing said control data in said processor in synchronization with the operation of said control means, and means for accessing said control storage means in order to read said control data.
Claim 2
Dependent Claim
198 words
A data input control system for reducing the number of terminals required by a processor without reducing the functionality of said processor comprising: a control storage means for storing control data integrated on a one-chip semiconductor device, a processor means integrated on another one-chip semiconductor device having input terminals for receiving said control data, means for generating a clock pulse, gating means for supplying said control data read out from said control storage to said processor means in response to said clock pulse, means for controlling said gating means on a time-division basis satisfying the following relationships ##EQU1## wherein A is the access time of said control storage; B is the memory cycle time of said control storage; C is the number of control data input terminals of said processor; D is the bit length of said control data; n is the number of division times of said control data in said memory cycle time B; and, T is the period of said clock pulse; means for storing said control data in said processor in synchronization with the operation of said control means, and means for accessing said control storage means in order to read said control data.
Claim 3
Dependent Claim
57 words
A data input control system according to claim 1, wherein: said controlling means includes a first shift register driven by said clock pulse; and, said storing means includes a second shift register driven by said clock pulse and a buffer register for sequentially storing said control data in synchronization with the operation of said second shift register.
Claim 4
Dependent Claim
31 words
A data input control system according to claim 2 wherein: said first and second shift registers are n-bit registers, said buffer register comprises an (n-1)-stage register with C-bit lengths per stage.
Claim 5
Dependent Claim
32 words
A data input control system according to claim 2, wherein: said processor further includes a control data register for storing said control data in synchronization with the operation said second shift register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-05-01 | 1981-10-31 | 1982-05-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-05-01 | 1985-10-31 | 1986-05-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-05-01 | 1989-10-31 | 1990-05-02 | $7700.00 | Window Closed / Lapsed |