Apparatus and method for generating a high-accuracy 7-level correlative signal

Claim 2

Apparatus for generating a 7-level correlative signal from a serial binary input signal comprising: means for changing said serial binary signal into two parallel binary bit streams, each at one-half the bit rate of the serial binary signal; means for encoding the two parallel binary bit streams to obtain correlation between a present digit and the second digit back from said present digit; means for digitally converting the encoded signal into a 7-level digital signal; and means for transforming said 7-level digital signal into a band-limited correlative 7-level analog signal related on a one-to-one basis to the binary input signal.

Claim 3

Apparatus in accordance with claim 1 wherein said means for encoding further comprises: timing means; gating means having a plurality of inputs connected to respective output of said changing means and providing a plurality of outputs; delay means having a plurality of inputs connected to the outputs of said gating means, having an input connected to said timing means, and providing a plurality of outputs having a delay of one time interval of the parallel bit streams and an equal number of outputs each having delays equal to two time intervals; and feedback means feeding back to said gating means selected outputs from said delay means.

Claim 4

Apparatus in accordance with claim 2 wherein said means for digitally converting further comprises; a second gating means having a like plurality of inputs connected to respective outputs of said encoding means, and having a plurality of outputs; and summing means having inputs for connection to the outputs of said second gating means, and an input connected to said timing means, said summing means providing a 7-level output signal.

Claim 5

Apparatus in accordance with claim 3 wherein said transforming means further comprises: a low-pass filter H(w) having an effective cutoff frequency which is substantially equal to 1/4 the bit rate of the original serial binary input signal.

Claim 8

Apparatus for generating a 7-level correlative signal from a serial binary input signal comprising: means for changing said serial binary input signal into two parallel binary bit streams, each at one-half the bit rate of the serial binary signal; means for encoding the two parallel binary bit streams to obtain binary outputs in accordance with the relation B = C - Δ.sup.2 C MOD 4 where B is the input waveform, C is the output waveform and Δ 2 indicates two intervals of delay or 2T seconds where 1/T is the one-half rate bit speed; means for digitally converting the encoded signal into a 7-level digital signal; and means for transforming said 7-level digital signal into a band-limited correlative 7-level analog signal related on a one-to-one basis to the binary input signal.

Claim 9

Apparatus for generating a 7-level correlative signal from a serial binary input signal comprising: means for changing said serial binary input signal into two parallel binary bit streams, each at one-half the bit rate of the serial binary signal; means for encoding the two parallel binary bit streams to obtain binary outputs in accordance with the relation B = C - Δ.sup.2 C MOD 4 where B is the input waveform, C is the output waveform and Δ 2 indicates two intervals of delay or 2T seconds where 1/T is the one-half rate bit speed; means for digitally converting the encoded signal into a 7-level digital signal; and means for transforming said 7-level digital signal into a band-limited correlative 7-level analog signal related on a one-to-one basis to the binary input signal.

Claim 10

Apparatus in accordance with claim 6 wherein said means for encoding further comprises: timing means; gating means having first and second inputs connected to receive the two parallel binary outputs from said changing means, and providing gated signals on first and second outputs; delay means having first and second inputs connected to the respective outputs of said encoding means, having an input connected to said timing means, having four binary outputs with one interval of delay and four outputs having two intervals of delay; and means for feeding back to said gating means selected two unit delayed binary signals.

Claim 11

Apparatus in accordance with claim 7 wherein said means for digitally converting further comprises: a second gating means having inputs connected to the 8 outputs from said encoding means, said gating means providing binary output signals; and summing means having 6 inputs connected to receive the gated output signals from the second gating means, having an input connected to said timing means, said summing means providing a 7-level output signal.

Claim 12

Apparatus in accordance with claim 8 wherein said transforming means further comprises: a low-pass filter H(w) having an effective cut-off frequency which is substantially equal to 1/4 the bit rate of the original serial binary input signal.

Claim 13

Apparatus in accordance with claim 9 wherein said summing means further comprises: six D-type flip-flops each having its D input connected to one output of said second gating means, having the T input connected to said timing means and providing Q and Q at the output of each flip-flop; twelve inverters one for each flip-flop output, each having its output connected to an associated flip-flop output, and each having an output; twelve equal valued resistors each having one end connectd to the output of one inverter, the other ends of the first three resistors associated with Q outputs of the first three flip-flops are connected together and these are connected together with the other end of the resistors associated with the Q outputs of the second three flip-flops, and this junction is one path; and, similarly the next three resistors have the one end connected to the outputs of the three inverters associated with the Q output of the first three flip-flops, the final three resistors have the one end connected to the outputs of the three inverters associated with the Q outputs of the last three flip-flops and the other ends of the second six resistors are joined together and this junction from the beginning of a second path; and a pair of equal valued resistors, the first resistor having one end connected to the first path, the second resistor having one end connected to the second path and the other ends of the two resistors connected together and connected to a common ground point.