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US4086471A
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Pulse train converter
Assignee: Toshiba Corp
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Filing: 1977-04-06
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Granted: 1978-04-25
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Expires: 1997-04-06
Abstract
Abstract A pulse train converter converts a first pulse train into a second pulse train of a higher frequency. The pulse train converter comprises a pulse generator for generating pulses having a specified frequency, a frequency divider for dividing the output frequency of the pulse generator by 2 M/n, where n denotes an integer and M denotes the number of parts into which the time period of the pulses contained in the first pulse train is divided by the pulses contained in the second pulse train, a counter which is reset upon receipt of each pulse of the first pulse train and starts to count the output pulses from the frequency divider, and a register for storing the count of the counter upon receipt of each pulse of the first pulse train. The lower order n bits of the output of the register are supplied to compensation signal generator circuit, and the remaining higher order bits are preset in a preset counter as a reference value. The preset counter produces pulses constituting the second pulse train, each time it receives from the pulse generator pulses the number of which is equal to the reference value. The compensation signal generator cumulates the lower order n bits. Each time the value of the cumulated lower order bits reaches a specified value, it supplies a compensation signal to the preset counter, thereby to compensate the reference value.
Inventors
- 👤 Yukiharu Takahashi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 05:11
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/60; G06F7/68; G06F7/62
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
215 words
A pulse train converter for converting a first pulse train into a second pulse train having a frequency higher than that of the first pulse train, comprising: a pulse generator for generating pulses having a specified frequency; a frequency divider for dividing the output frequency of the pulse generator by (M/2 n ), where n denotes an integer and M denotes the number of parts into which the time period of the pulses contained in said first pulse train is divided by the pulses contained in said second pulse train; a counter which is reset upon receipt of each pulse of said first pulse train and starts to count the output pulses supplied from said frequency divider, a register for storing the count of said counter upon receipt of each pulse of said first pulse train; a pulse delivering means which receives only the remaining higher order bits except lower order n bits of the count stored in said register as a reference value and which delivers pulses constituting said second pulse train each time the number of pulses it receives from said pulse generator equals the reference value; and a compensation means for compensating said reference value in accordance with the count value represented by said lower order n bits supplied from said register.
Claim 2
Dependent Claim
215 words
A pulse train converter for converting a first pulse train into a second pulse train having a frequency higher than that of the first pulse train, comprising: a pulse generator for generating pulses having a specified frequency; a frequency divider for dividing the output frequency of the pulse generator by (M/2 n ), where n denotes an integer and M denotes the number of parts into which the time period of the pulses contained in said first pulse train is divided by the pulses contained in said second pulse train; a counter which is reset upon receipt of each pulse of said first pulse train and starts to count the output pulses supplied from said frequency divider, a register for storing the count of said counter upon receipt of each pulse of said first pulse train; a pulse delivering means which receives only the remaining higher order bits except lower order n bits of the count stored in said register as a reference value and which delivers pulses constituting said second pulse train each time the number of pulses it receives from said pulse generator equals the reference value; and a compensation means for compensating said reference value in accordance with the count value represented by said lower order n bits supplied from said register.
Claim 3
Dependent Claim
52 words
The pulse train converter according to claim 1, wherein said compensation means includes an n-bit adder which cumulates said lower order n bits supplied from said register and which supplies a compensation signal for compensating said reference value to said pulse delivering means each time the cumulated count reaches a predetermined value.
Claim 4
Dependent Claim
86 words
The pulse train converter according to claim 1, wherein said compensation means includes an n-bit counter which counts the output pulses of said pulse delivering means and a logic circuit which receives the output of said n-bit counter and said lower order n bits supplied from said register and which supplies a compensation signal for compensating said reference value to said pulse delivering means each time the output of said n-bit counter has a predetermined relationship with said lower order n bits supplied from said register.
Claim 5
Dependent Claim
19 words
The pulse train converter according to claim 1, wherein said pulse delivering means is constituted by a preset counter.
Claim 6
Dependent Claim
251 words
A pulse train converter for converting a first pulse train into a second pulse train having a frequency higher than that of the first pulse train, comprising: a pulse generator for generating pulses having a specified frequency; a first frequency divider for dividing the output frequency of said pulse generator by M, where M denotes the number of parts into which the time period of the pulses contained in said first pulse train is divided by the pulses contained in said second pulse train; a counter which receives the pulses of said first pulse train and the output pulses from said first frequency divider and which is reset upon receipt of each pulse of said first pulse train and starts to count the output pulses supplied from said first frequency divider; a register for storing the count of said counter upon receipt of each pulse of said first pulse train; a second frequency divider for dividing the output frequency of said pulse generator by 2 n , where n denotes an integer; a pulse delivering means which receives only the higher order bits except lower order n bits of the count stored in said register as a reference value and which delivers pulses constituting said second pulse train each time the number of pulses it receives from said second frequency divider equals said reference value; and a compensation means for compensating said reference value in accordance with the count value represented by the lower order n bits supplied from said register.
Claim 7
Dependent Claim
251 words
A pulse train converter for converting a first pulse train into a second pulse train having a frequency higher than that of the first pulse train, comprising: a pulse generator for generating pulses having a specified frequency; a first frequency divider for dividing the output frequency of said pulse generator by M, where M denotes the number of parts into which the time period of the pulses contained in said first pulse train is divided by the pulses contained in said second pulse train; a counter which receives the pulses of said first pulse train and the output pulses from said first frequency divider and which is reset upon receipt of each pulse of said first pulse train and starts to count the output pulses supplied from said first frequency divider; a register for storing the count of said counter upon receipt of each pulse of said first pulse train; a second frequency divider for dividing the output frequency of said pulse generator by 2 n , where n denotes an integer; a pulse delivering means which receives only the higher order bits except lower order n bits of the count stored in said register as a reference value and which delivers pulses constituting said second pulse train each time the number of pulses it receives from said second frequency divider equals said reference value; and a compensation means for compensating said reference value in accordance with the count value represented by the lower order n bits supplied from said register.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-04-24 | 1981-10-24 | 1982-04-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-04-24 | 1985-10-24 | 1986-04-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-04-24 | 1989-10-24 | 1990-04-25 | $7700.00 | Window Closed / Lapsed |