Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
203 words
In a full duplex data transmission system having subscriber stations interconnected by two wire lines, each subscriber station having a transmitter and a receiver, a circuit arrangement in each said subscriber station for automatically adjusting the value of current conducted from the transmitter in a given station to receive therein relative to the value of a received current transmitted from another of said stations, the circuit arrangement comprising: balancing circuit means coupling current from said transmitter in the given station to the receiver therein, said balancing circuit comprising a plurality of branch circuits for dividing said transmitter current into a plurality of sub-currents, said sub-currents being recombined prior to coupling to said receiver, each said branch circuit being a series combination of a voltage responsive current adjusting means and a timing circuit, comparison means for receiving said transmitter current as supplied from said balancing circuit means and said received current and for producing an output voltage having a value proportional to the difference between the values of said transmitter current and said received current, and regulating circuit means for producing, responsive to said comparison means output voltage, regulating voltages coupled, respectively, to said current adjusting means for controlling the values of said sub-currents.
Claim 2
Dependent Claim
203 words
In a full duplex data transmission system having subscriber stations interconnected by two wire lines, each subscriber station having a transmitter and a receiver, a circuit arrangement in each said subscriber station for automatically adjusting the value of current conducted from the transmitter in a given station to receive therein relative to the value of a received current transmitted from another of said stations, the circuit arrangement comprising: balancing circuit means coupling current from said transmitter in the given station to the receiver therein, said balancing circuit comprising a plurality of branch circuits for dividing said transmitter current into a plurality of sub-currents, said sub-currents being recombined prior to coupling to said receiver, each said branch circuit being a series combination of a voltage responsive current adjusting means and a timing circuit, comparison means for receiving said transmitter current as supplied from said balancing circuit means and said received current and for producing an output voltage having a value proportional to the difference between the values of said transmitter current and said received current, and regulating circuit means for producing, responsive to said comparison means output voltage, regulating voltages coupled, respectively, to said current adjusting means for controlling the values of said sub-currents.
Claim 3
Dependent Claim
106 words
The circuit arrangement defined in claim 1 wherein said regulating means comprises: a number of multiplier circuits equal to the number of said branch circuits, each said multiplier circuit being assigned to a said branch circuit and being connected at its inputs to receive and produce a product signal from said comparison means output voltage and the output from the said timing circuit in the assigned branch circuit, and a number of integrators, one of which is connected to the output of each said multiplier, the outputs of said integrators being connected, respectively, to control inputs of said current regulating means in the assigned branch circuits.
Claim 4
Dependent Claim
35 words
The circuit arrangement defined in claim 1 wherein in each said branch circuit, relative to the direction of current flow of said transmitter current, said current regulating means is arranged downstream of said timing circuit.
Claim 5
Dependent Claim
71 words
The circuit arrangement defined in claim 1 wherein in each said branch circuit, relative to the direction of current flow of said transmitter current, said timing circuit is arranged downstream of said current regulating means and further comprising: a number of additional timing circuits equal to the number of said branch circuits, one of said additional timing circuits connecting each said branch circuit to an input of said regulating circuit means.