US4052556A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement for balancing a two wire full duplex data transmission system
Assignee: Siemens AG
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Filing: 1975-10-28
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Granted: 1977-10-04
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Expires: 1995-10-28
Abstract
Abstract Apparatus is described for balancing a two wire, full duplex data transmission system. In the described system a transmitter and receiver in one station are connected to a transmitter and receiver in another station by means of two lines. The two lines carry transmitted data signals, and the transmitters in each station are connected to the receiver in the same station by a dummy circuit. The balancing operation is performed in a dummy circuit comprising a plurality of parallel-connected current paths, each path including a series combination of a time stage and an amplitude stage for adjusting the amplitude and phase relation to the data signal of subsidiary current flowing therethrough. The sum of the subsidiary currents flowing through the parallel paths from the transmitter via the dummy circuit to the receiver in the same station is adjusted to be equal to the current flowing from the transmitter via the lines to the receiver in the same station.
Inventors
- 👤 Adolf Haass
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 20:46
CPC Classifications
H; H04; H04L; H04L5/00; H04L5/14; H04L5/1423
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
227 words
In a two wire, full duplex data transmission system wherein a transmitter and receiver in one station are connected by two wires to a transmitter and receiver in another station, the transmitter in each station being connected by means of a balancing apparatus to the receiver therein for adjusting the value of the current from the transmitter flowing through said two wires to the receiver in the same station to be equal to current flowing from the transmitter directly to the receiver in said another station, the balancing apparatus comprising. a plurality of parallel-connected current paths, each comprising a series combination of a time stage and an amplitude stage, said parallel-connected current paths being connected to received current from the transmitter in the same station, a plurality of subsidiary currents flowing through said parallel current paths to a common output terminal which couples a sum current of said subsidiary currents to the receiver in the same station, each said time stage being constructed to produce predetermined, but different, timing signals in relation to a data signal being transmitted from the station, said amplitude stages being constructed to adjust the values of said subsidiary currents flowing therethrough and said time and amplitude stages having a connected relationship such that each said amplitude stage is effective for a duration determined by the timing signal from the associated time stage.
Claim 2
Dependent Claim
227 words
In a two wire, full duplex data transmission system wherein a transmitter and receiver in one station are connected by two wires to a transmitter and receiver in another station, the transmitter in each station being connected by means of a balancing apparatus to the receiver therein for adjusting the value of the current from the transmitter flowing through said two wires to the receiver in the same station to be equal to current flowing from the transmitter directly to the receiver in said another station, the balancing apparatus comprising. a plurality of parallel-connected current paths, each comprising a series combination of a time stage and an amplitude stage, said parallel-connected current paths being connected to received current from the transmitter in the same station, a plurality of subsidiary currents flowing through said parallel current paths to a common output terminal which couples a sum current of said subsidiary currents to the receiver in the same station, each said time stage being constructed to produce predetermined, but different, timing signals in relation to a data signal being transmitted from the station, said amplitude stages being constructed to adjust the values of said subsidiary currents flowing therethrough and said time and amplitude stages having a connected relationship such that each said amplitude stage is effective for a duration determined by the timing signal from the associated time stage.
Claim 3
Dependent Claim
50 words
The balancing apparatus defined in claim 1 wherein the inputs of said time stages are connected to the transmitter in the same station and the outputs of said time stages are connected to inputs of said amplitude stages, the outputs of said amplitude stages being connected to said output terminal.
Claim 4
Dependent Claim
44 words
The balancing apparatus defined in claim 1 wherein inputs of said amplitude stages are connected to said transmitter and outputs of said amplitude stages are connected to inputs of said time stages, the outputs of said time stages being connected to said output terminal.
Claim 5
Dependent Claim
33 words
The balancing apparatus defined in claim 1 wherein said time stages are connected to operate responsively to the data signal and operate to emit time signals which commence simultaneously and have different durations.
Claim 6
Dependent Claim
50 words
The balancing apparatus defined in claim 1 wherein said time stages are connected operate responsively to the data signal and operate to emit a sequence of time signals which do not overlap, the first of said time signals occurring after the occurrence of the leading edge of the data signal.
Claim 7
Dependent Claim
17 words
The balancing apparatus defined in claim 3 wherein said amplitude stages produce amplitude signals of equal duration.
Claim 8
Dependent Claim
21 words
The balancing apparatus defined in claim 1 wherein each said time stage comprises a RC circuit have a predetermined time constant.
Claim 9
Dependent Claim
42 words
The balancing apparatus defined in claim 7 wherein each said amplitude stage comprises a series resistor connected to a parallel potentiometer, the maximum resistances of said potentiometers being no greater than one-tenth of the values of the resistances in said time stages.
Claim 10
Dependent Claim
114 words
The balancing apparatus defined in claim 1 wherein said time stages comprise: a shift register having a sequence of cells which assume a rest state or an operative state, the rest state being assumed before the occurrence of the data signal, a pulse generator connected to the first cell in said sequence for emitting pulses to advance an item of information through said shift register, the outputs of said cells being connected, respectively, to amplitude stages in different ones of said current paths, differentiator means for receiving the data signal from the transmitter and for coupling the data signal to said first cell upon the occurrence of a leading edge of said data signal.
Claim 11
Dependent Claim
58 words
The balancing apparatus defined in claim 1 wherein each said amplitude stage comprises: an operational amplifier having an output, an inverting input and a non-inverting input, said non-inverting input being connected to a reference potential, a potentiometer connecting said inverting input to said output of said operational amplifier, and a resistance connecting said inverting input to the transmitter.
Claim 12
Dependent Claim
199 words
The balancing apparatus defined in claim 1 further comprising: first threshold circuit means for producing a first binary signal when a measuring current dependent said sum current and the current flowing into said receiver from a said wire exceeds a first threshold value, second threshold circuit means for producing a second binary signal when said measuring current undershoots a second threshold value, a source of time signals, responsive to the data signal, a first group of AND gates, each gate having one input connected to said time signal source and another input connected to the output of said first threshold circuit means, a second group of AND gates, each having one input connected to said timing signal source and another input connected to the output of said second threshold circuit means, first and second groups of stores, the inputs of said first group of stores being connected, respectively, to outputs of said first group of AND gates and inputs of said second group of stores being connected, respectively, to outputs of said second group of AND gates, indicating means operable responsive to the binary states of said stores for indicating which of said stores are in an operative state.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-10-03 | 1981-04-04 | 1981-10-04 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-10-03 | 1985-04-04 | 1985-10-04 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-10-03 | 1989-04-04 | 1989-10-04 | $7700.00 | Window Closed / Lapsed |