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US4085458A
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Random access memory
Assignee: Hitachi Ltd
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Filing: 1976-05-26
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Granted: 1978-04-18
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Expires: 1996-05-26
Abstract
Abstract In a n-channel (or p-channel) random access memory in which a plurality of memory cells are arranged in a matrix form in a p-type (or n-type) semiconductor substrate, clamping MOSFET's are connected between word lines provided for the associated rows of memory cells of the matrix and a reference potential to which gates the source electrodes of the information storing MOSFET's of the memory cells are connected. The clamping MOSFET has a lower threshold voltage than a row selecting MOSFET connected to the word line and clamps the word line when the word line is not selected, so that a delay in the read-out operation is eliminated or suppressed.
Inventors
- 👤 Kunihiko Ikuzaki
- 👤 Tsuneo Ito
- 👤 Masamichi Ishihara
- 👤 Takashi Sato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 14:13
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/403; G11C11/405
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
146 words
An n-channel random access memory comprising in a p-type semiconductor substrate: a plurality of memory cells arranged in a matrix form, each of the memory cells including an information storing MOSFET having a source connected to a reference potential, word lines being associated with respective rows of the matrix, the word line being adapted to receive a positive voltage signal relative to the reference potential; row selecting MOSFET's connected to the word lines respectively; and switching means including a plurality of clamping MOSFET's each connected between a respective word line and said reference potential for clamping the word line to a predetermined potential when the word line is not selected, said clamping MOSFET's having a lower threshold voltage than that of the row selecting MOSFET to thereby turn on prior to the row selecting MOSFET in response to a noise signal on the non-selected word line.
Claim 2
Dependent Claim
146 words
An n-channel random access memory comprising in a p-type semiconductor substrate: a plurality of memory cells arranged in a matrix form, each of the memory cells including an information storing MOSFET having a source connected to a reference potential, word lines being associated with respective rows of the matrix, the word line being adapted to receive a positive voltage signal relative to the reference potential; row selecting MOSFET's connected to the word lines respectively; and switching means including a plurality of clamping MOSFET's each connected between a respective word line and said reference potential for clamping the word line to a predetermined potential when the word line is not selected, said clamping MOSFET's having a lower threshold voltage than that of the row selecting MOSFET to thereby turn on prior to the row selecting MOSFET in response to a noise signal on the non-selected word line.
Claim 3
Dependent Claim
146 words
A p-channel random access memory comprising in an n-type semiconductor substrate: a plurality of memory cells arranged in a matrix form, each of the memory cells including an information storing MOSFET having a source connected to a reference potential, word lines being associated with respective rows of the matrix, the word line being adapted to receive a negative voltage signal relative to the reference potential; row selecting MOSFET's connected to the word lines respectively; and switching means including a plurality of clamping MOSFET's each connected between a respective word line and said reference potential for clamping the word line to a predetermined potential when the word line is not selected, the clamping MOSFET's having a lower threshold voltage than that of the row selecting MOSFET to thereby turn on prior to the row selecting MOSFET in response to a noise signal on the non-selected word line.
Claim 4
Dependent Claim
146 words
A p-channel random access memory comprising in an n-type semiconductor substrate: a plurality of memory cells arranged in a matrix form, each of the memory cells including an information storing MOSFET having a source connected to a reference potential, word lines being associated with respective rows of the matrix, the word line being adapted to receive a negative voltage signal relative to the reference potential; row selecting MOSFET's connected to the word lines respectively; and switching means including a plurality of clamping MOSFET's each connected between a respective word line and said reference potential for clamping the word line to a predetermined potential when the word line is not selected, the clamping MOSFET's having a lower threshold voltage than that of the row selecting MOSFET to thereby turn on prior to the row selecting MOSFET in response to a noise signal on the non-selected word line.
References Cited (Backward Citations)
US3980899A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-04-17 | 1981-10-17 | 1982-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-04-17 | 1985-10-17 | 1986-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-04-17 | 1989-10-17 | 1990-04-18 | $7700.00 | Window Closed / Lapsed |