US4085457A
Expired / Lapsed
US
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Memory system with a sense circuit
Assignee: Hitachi Ltd
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Filing: 1976-03-31
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Granted: 1978-04-18
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Expires: 1996-03-31
Abstract
Abstract In a memory system comprised of a memory array having a plurality of first data lines each of which has a plurality of memory cells connected thereto and a sense circuit for discriminating the information in the memory cells, the sense circuit includes a pair of second data lines, a pair of switching elements for selectively connecting two first data lines on the memory array with the pair of second data lines in response to applied address signals, and a sense amplifier comprising a flip-flop circuit having two input nodes connected to said pair of second data lines.
Inventors
- 👤 Kiyoo Itoh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 15:43
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/4063; G11C11/407; G11C11/409; G11C11/4093; G11C11/403; G11C11/404; G11C5/00; G11C5/02; G11C5/025
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
96 words
A memory system comprising: first and second data lines, to each of which a plurality of memory cells for storing information are connected; third and fourth data lines; first and second switching means for individually connecting said first and second data lines on a selective basis to said third and fourth data lines, respectively, in response to respective first and second address signals respectively applied to said first and second switching means; and a sense amplifier comprised of a flip-flop circuit having first and second input nodes connected to said third and fourth data lines, respectively.
Claim 2
Dependent Claim
96 words
A memory system comprising: first and second data lines, to each of which a plurality of memory cells for storing information are connected; third and fourth data lines; first and second switching means for individually connecting said first and second data lines on a selective basis to said third and fourth data lines, respectively, in response to respective first and second address signals respectively applied to said first and second switching means; and a sense amplifier comprised of a flip-flop circuit having first and second input nodes connected to said third and fourth data lines, respectively.
Claim 3
Dependent Claim
49 words
A memory system according to claim 1, which further comprises first and second common writing data lines, and third and fourth switching means for selectively connecting said first and second common writing data lines to said third and fourth data lines, respectively, in response to a writing control signal.
Claim 4
Dependent Claim
87 words
A memory system according to claim 1, in which said first switching means includes a first MOS transistor having an input terminal to which said first address signal is applied, and first and second output terminals which are connected to said first and third data lines, respectively; and wherein said second switching means includes a second MOS transistor having an input terminal to which said second address signal is applied, and first and second output terminals which are connected to said second and fourth data lines, respectively.
Claim 5
Dependent Claim
21 words
A memory system according to claim 1, wherein said first and second data lines are arranged on the respective memory arrays.
Claim 6
Dependent Claim
146 words
A memory system according to claim 1, in which said flip-flop circuit comprises first, second, third and fourth MOS transistors, each having an input terminal and first and second output terminals, said first output terminals of said first and second MOS transistors being connected in common to said first input node and said input terminal of said third MOS transistor, and said first output terminals of said third and fourth MOS transistors being connected in common to said second input node and said input terminal of said first MOS transistor, means for applying a source voltage to said second output terminals of said second and fourth MOS transistors, means for applying a first control voltage to said input terminals of said second and fourth MOS transistors, and means for applying a second control voltage to said second output terminals of said first and third MOS transistors.
Claim 7
Dependent Claim
43 words
A memory system according to claim 5, in which each of said first and second data lines includes a pair of data line portions, and which further comprises a preamplifier having respective first and second input nodes connected to said data line portions.
Claim 8
Dependent Claim
52 words
A memory system according to claim 6, which further comprises first and second common sensing data lines and a second sense amplifier connected between said third and fourth data lines and said first and second common sensing data lines for applying amplified signals to said first and second common sensing data lines.
Claim 9
Dependent Claim
49 words
A memory system according to claim 6, which further comprises first and second common writing data lines, and third and fourth switching means for selectively connecting said first and second common writing data lines to said third and fourth data lines, respectively, in response to a writing control signal.
Claim 10
Dependent Claim
86 words
A memory system according to claim 8, wherein said first switching means includes a fifth MOS transistor having an input terminal to which said first address signal is applied, and first and second output terminals which are connected to said first and third data lines, respectively; and wherein said second switching means includes a sixth MOS transistor having an input terminal to which said second address signal is applied, and first and second output terminals which are connected to said second and fourth data lines, respectively.
Claim 11
Dependent Claim
43 words
A memory system according to claim 1, in which each of said first and second data lines includes a pair of data line portions, and which further comprises a preamplifier having respective first and second input nodes connected to said data line portions.
Claim 12
Dependent Claim
64 words
A memory system according to claim 10, wherein a plurality of memory cells and a dummy cell are connected to each of said data line portions so that, when information in one memory cell connected to one of said data line portions is read out, information in the dummy cell connected to the other data line portion is read out as a reference signal.
Claim 13
Dependent Claim
52 words
A memory system according to claim 1, which further comprises first and second common sensing data lines and a second sense amplifier connected between said third and fourth data lines and said first and second common sensing data lines for applying amplified signals to said first and second common sensing data lines.
Claim 14
Dependent Claim
92 words
A memory system according to claim 12, wherein each of said first and second data lines includes a pair of data line portions, to each of which a plurality of memory cells and a dummy cell are connected so that, when information in one memory cell connected to one of said data line portions is read out, information in the dummy cell connected to the other data line portion is read out as a reference signal, and a preamplifier having respective first and second input nodes connected to said data line portions.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-04-17 | 1981-10-17 | 1982-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-04-17 | 1985-10-17 | 1986-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-04-17 | 1989-10-17 | 1990-04-18 | $7700.00 | Window Closed / Lapsed |