Computer programming system having greatly reduced storage capacity and high speed

Claim 2

A programming system for programming a computer means comprising: a. switching means; b. a main programming memory device for containing groups of data which are readout therefrom and applied to said computer means by said switching means for causing said computer means to execute a selected instruction with respect to arithmetic data processed therein; c. auxiliary function means for generating logic data unique to a particular instruction being executed; d. an instruction designation signal source for designating a particular instruction to be applied to said computer means; e. coupling means coupled between said instruction designation signal source and said auxiliary function means for controlling the generation of said unique logic data by said auxiliary function means in accordance with the designation of a selected instruction by said signal source; f. data source selection means, associated with logic data cells within said main programming memory, for producing a first signal upon readout when logic data within associated logic data cells is not unique to a particular instruction being executed and for producing a second signal upon readout when logic data within associated logic data cells is unique to a particular instruction being executed; and g. switch control means, coupled to said switching means, for causing logic data within said main programming memory to be transmitted by said switching means to said computer means when said data source selection means produces said first signal upon readout, and for causing said logic data generated by said auxiliary function means to be transmitted to said computer means by said switching means rather than data from said main programming memory, when said source selection means produces said second signal upon readout.

Claim 3

The combination as set forth in claim 1 wherein said data source selection means comprises a cell within said main programming memory having data therein for selectively producing said first or said second signal upon readout.

Claim 4

The combination as set forth in claim 2 wherein said main programming memory comrpises a PROM device.

Claim 5

The combination as set forth in claim 1 wherein said switch control means further comprises a first gate for transmitting data from said main programming memory to said computer means, a second gate for transmitting data from said auxiliary function means to said computer means and inverter means for disabling one of said gates upon the enabling of the other of said gates.

Claim 6

The combination as set forth in claim 2 wherein said switch control means further comprises a first gate for transmitting data from said main programming memory to said computer means, a second gate for transmitting data from said auxiliary function means to said computer means and inverter means for disabling one of said gates upon the enabling of the other of said gates.

Claim 7

The combination as set forth in claim 3 wherein said switch control means further comprises a first gate for transmitting data from said main programming memory to said computer means, a second gate for transmitting data from said auxiliary function means to said computer means and inverter means for disabiling one of said gates upon the enabling of the other of said gates.

Claim 8

A programming system for programming a computer means comprising: a. switching means; b. a main programming memory device for containing groups of data which are sequentially readout therefrom and applied to said computer means by said switching means for causing said computer means to execute a selected instruction with respect to arithmetic data processed therein; c. an auxiliary function memory having a plurality of cells therein, each of which contains logic data unique to a particular instruction being executed; d. an instruction designation signal source for designating a particular instruction to be applied to said computer means; e. coupling means coupled between said instruction designation signal source and said auxiliary functon memory for addressing a particular cell within said auxiliary function memory corresponding to the particular instruction designated by said instruction designation signal source; f. data source selection cells associated with logic data cells within said main programming memory, for producing a first signal upon readout when logic data within associated logic data cells is not unique to a particular instruction being executed, and for producing a second signal upon readout when logic data within associated logic data cells is unique to a particular instruction being executed; and g. switch control means, coupled to said switching means, for causing logic data within said main programming memory to be transmitted by said switching means to said computer means when the data within said source selection cells, associated with logic cells containing non-unique logic data, produce said first signal upon readout, and for causing the unique logic data within the addressed cell of said auxiliary function memory to be transmitted to said computer means by said switching means rather than data from said main programming memory, when the source selection cells contain data for producing said second signal upon readout.

Claim 9

A programming system for programming a computer means comprising: a. switching means; b. a main programming memory device for containing groups of data which are sequentially readout therefrom and applied to said computer means by said switching means for causing said computer means to execute a selected instruction with respect to arithmetic data processed therein; c. an auxiliary function memory having a plurality of cells therein, each of which contains logic data unique to a particular instruction being executed; d. an instruction designation signal source for designating a particular instruction to be applied to said computer means; e. coupling means coupled between said instruction designation signal source and said auxiliary functon memory for addressing a particular cell within said auxiliary function memory corresponding to the particular instruction designated by said instruction designation signal source; f. data source selection cells associated with logic data cells within said main programming memory, for producing a first signal upon readout when logic data within associated logic data cells is not unique to a particular instruction being executed, and for producing a second signal upon readout when logic data within associated logic data cells is unique to a particular instruction being executed; and g. switch control means, coupled to said switching means, for causing logic data within said main programming memory to be transmitted by said switching means to said computer means when the data within said source selection cells, associated with logic cells containing non-unique logic data, produce said first signal upon readout, and for causing the unique logic data within the addressed cell of said auxiliary function memory to be transmitted to said computer means by said switching means rather than data from said main programming memory, when the source selection cells contain data for producing said second signal upon readout.

Claim 10

The combination as set forth in claim 7 wherein said data source selection means comprises a single cell within said main programming memory having a single bit therein for selectively producing said first or said second signal upon readout.

Claim 11

The combination as set forth in claim 8 wherein said main programming memory comrpises a PROM device.

Claim 12

The combination as set forth in claim 7 wherein said switch control means further comrprises a first gate for transmitting data from said main programming memory to said computer means, a second gate for transmitting data from said auxiliary function means to said computer means and inverter means for disabiling one of said gates upon the enabling of the other of said gates.

Claim 13

The combination as set forth in claim 8 wherein said switch control means further comprises a first gate for transmitting data from said main programming memory to said computer means, a second gate for transmitting data from said auxiliary function means to said computer means and inverter means for disabling one of said gates upon the enabling of the other of said gates.

Claim 14

The combination as set forth in claim 9 wherein said switch control means further comprises a first gate for transmitting data from said main programming memory to said computer means, a second gate for transmitting data from said auxiliary function means to said computer means and inverter means for disabling one of said gates upon the enabling of the other of said gates.