Patent US4196147A successfully refreshed from Google Patents.
Patent US4085339A successfully refreshed from Google Patents.
US4085339A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Circuit arrangement in a complementary CHL technique
Assignee: Siemens AG
•
Filing: 1975-09-29
•
Granted: 1978-04-18
•
Expires: 1995-09-29
Abstract
Abstract A circuit arrangement CHL technique (current hogging logic) includes individual CHL arrangements each having an emitter, control collectors and an output collector and arranged within an epitaxial layer. The individual CHL arrangements are complementary with respect to one another, and arrangement of one conductivity type being directly integrated in the epitaxial layer and the arrangement which is complementary thereto being integrated in a basin in the epitaxial layer, the basin being doped opposite to the epitaxial layer.
Inventors
- 👤 Karl Goser
- 👤 Ruediger Mueller
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 15:58
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/60; H10D84/65; H10D99/00
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
298 words
A current hogging logic circuit arrangement comprising: a body of semiconductor material having a first portion of a first conductivity type and a second portion of a second conductivity type; a first multi-collector bipolar transistor formed in said first portion of said body, said first portion of a first conductivity type forming the base region of said first transistor, a first emitter region of second conductivity type formed in said first portion, a first output collector region of second conductivity type formed in said first portion spaced from said first emitter region, and a first control collector region of second conductivity type formed in said first portion, said first control collector region located between and spaced from said first emitter region and said first output collector region, a second multi-collector bipolar transistor formed in said second portion of said body, said second portion of said second conductivity type forming the base region of said second transistor, a second emitter region of first conductivity type formed in said second portion, a second output collector region of said first conductivity type formed in said second portion spaced from said second emitter region, and a second control collector region of first conductivity type formed in said second portion spaced from said second emitter region, said second control collector region located between and spaced from said second emitter region and said second output collector region; means for forward-biasing the pn junction between said first portion and said first emitter region; and means for forward-biasing the pn junction between said second portion and said second emitter region, said first control collector region being directly connected to said second output collector region, whereby current flow through said first output collector region may be controlled by controlling current flow through said second control collector region.
Claim 2
Dependent Claim
298 words
A current hogging logic circuit arrangement comprising: a body of semiconductor material having a first portion of a first conductivity type and a second portion of a second conductivity type; a first multi-collector bipolar transistor formed in said first portion of said body, said first portion of a first conductivity type forming the base region of said first transistor, a first emitter region of second conductivity type formed in said first portion, a first output collector region of second conductivity type formed in said first portion spaced from said first emitter region, and a first control collector region of second conductivity type formed in said first portion, said first control collector region located between and spaced from said first emitter region and said first output collector region, a second multi-collector bipolar transistor formed in said second portion of said body, said second portion of said second conductivity type forming the base region of said second transistor, a second emitter region of first conductivity type formed in said second portion, a second output collector region of said first conductivity type formed in said second portion spaced from said second emitter region, and a second control collector region of first conductivity type formed in said second portion spaced from said second emitter region, said second control collector region located between and spaced from said second emitter region and said second output collector region; means for forward-biasing the pn junction between said first portion and said first emitter region; and means for forward-biasing the pn junction between said second portion and said second emitter region, said first control collector region being directly connected to said second output collector region, whereby current flow through said first output collector region may be controlled by controlling current flow through said second control collector region.
Claim 3
Dependent Claim
30 words
A current hogging logic circuit arrangement according to claim 1, constructed as a flip-flop, comprising a direct connection between said first output collector region and said second control collector region.
Claim 4
Dependent Claim
26 words
A current hogging logic circuit arrangement, according to claim 1, wherein said body of semiconductor material is an epitaxial silicon layer carried on an insulating substrate.
Claim 5
Dependent Claim
42 words
A current hogging logic circuit arrangement according to claim 1, comprising: a selection element connected to said output collector region of said first transistor and said control collector region of said second transistor; and a bit line connected to said selection element.
Claim 6
Dependent Claim
49 words
A current hogging logic circuit arrangement according to claim 4, wherein said selection element comprises a transistor having a base connected to said output collector zone of said first transistor, a collector connected to said base region of said first transistor, and an emitter connected to said bit line.
Claim 7
Dependent Claim
38 words
A current hogging logic circuit arrangement according to claim 4, wherein said selection element comprises a diode having an anode connected to said output collector region of said first transistor and a cathode connected to said bit line.
Claim 8
Dependent Claim
48 words
A current hogging logic circuit arrangement according to claim 1, wherein said body of semiconductor material comprises an epitaxial silicon layer carried on an insulating substrate, said epitaxial layer is an n-epitaxial layer, said first transistor is a pnp transistor, and said second transistor is an npn transistor.
Claim 9
Dependent Claim
49 words
A current hogging logic circuit arrangement according to claim 1, wherein said body of semiconductor material comprises an epitaxial silicon layer carried on an insulating substrate, wherein said epitaxial layer is a p-epitaxial layer, said first transistor is an npn transistor, and said second transistor is a pnp transistor.
References Cited (Backward Citations)
US3356858A
Cited
US3919765A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-04-17 | 1981-10-17 | 1982-04-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-04-17 | 1985-10-17 | 1986-04-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-04-17 | 1989-10-17 | 1990-04-18 | $7700.00 | Window Closed / Lapsed |