Patent US4084173A successfully refreshed from Google Patents.
US4084173A
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Interdigitated transistor pair
Assignee: Texas Instruments Inc
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Filing: 1976-07-23
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Granted: 1978-04-11
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Expires: 1996-07-23
Abstract
Abstract A pair of field effect transistors are arranged with interdigitated electrodes to reduce the voltage offset which can otherwise arise when the pair are operated as a differential amplifier. The interdigitated electrodes are arranged as essentially parallel elongated regions in a semiconductive substrate, certain regions serving as a first electrode for one of the field effect transistors, other regions serving as a first electrode for the other field effect transistor and still other regions serving as a common second electrode for both field effect transistors.
Inventors
- 👤 Roberto Luigi Fantechi
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:58
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/80; H10D84/82; H10D84/83; H10D84/83125
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
230 words
A complementary transistor pair device comprising: (a) a semiconductive substrate of semiconductive material selected from intrinsic or one conductivity type semiconductive material; (b) a plurality of first semiconductive regions of opposite conductivity type in said substrate and extending to a major surface thereof, said first semiconducting regions forming elongated areas in the surface of semiconductive substrate, the major axes thereof being essentially parallel and said first semiconductive regions being electrically interconnected; (c) a plurality of second semiconductive regions of said opposite conductivity type in said substrate, said second semiconductive regions forming elongated areas in the surface of said substrate, the major axes thereof being essentially parallel and said second semiconductive regions being electrically interconnected; (d) a plurality of third semiconductive regions of said opposite conductivity type in said substrate, said third semiconductive regions forming elongated areas in the surface of said substrate, the major axes thereof being essentially parallel, said third semiconductive regions being electrically interconnected and interdigitated with said first and second semiconductive regions; (e) a plurality of first gate electrodes, each of said first gate electrodes being disposed over a major portion of each of said first semiconductive regions, said first gate electrodes being electrically interconnected; and (f) a plurality of second gate electrodes, each of said second gate electrodes being disposed over a major portion of said second semiconducting regions, said second gate electrodes being electrically interconnected.
Claim 2
Dependent Claim
230 words
A complementary transistor pair device comprising: (a) a semiconductive substrate of semiconductive material selected from intrinsic or one conductivity type semiconductive material; (b) a plurality of first semiconductive regions of opposite conductivity type in said substrate and extending to a major surface thereof, said first semiconducting regions forming elongated areas in the surface of semiconductive substrate, the major axes thereof being essentially parallel and said first semiconductive regions being electrically interconnected; (c) a plurality of second semiconductive regions of said opposite conductivity type in said substrate, said second semiconductive regions forming elongated areas in the surface of said substrate, the major axes thereof being essentially parallel and said second semiconductive regions being electrically interconnected; (d) a plurality of third semiconductive regions of said opposite conductivity type in said substrate, said third semiconductive regions forming elongated areas in the surface of said substrate, the major axes thereof being essentially parallel, said third semiconductive regions being electrically interconnected and interdigitated with said first and second semiconductive regions; (e) a plurality of first gate electrodes, each of said first gate electrodes being disposed over a major portion of each of said first semiconductive regions, said first gate electrodes being electrically interconnected; and (f) a plurality of second gate electrodes, each of said second gate electrodes being disposed over a major portion of said second semiconducting regions, said second gate electrodes being electrically interconnected.
Claim 3
Dependent Claim
33 words
The device according to claim 1, wherein said plurality of electrically interconnected first gate electrodes provide a first gate and wherein said plurality of electrically interconnected second gate electrodes provide a second gate.
Claim 4
Dependent Claim
31 words
The device according to claim 2, wherein said first and second gates are further respectively disposed over portions of said semiconductive substrate adjacent to the interdigitated first and second semiconductive regions.
Claim 5
Dependent Claim
24 words
The device according to claim 1, further including a layer of insulating material disposed between said substrate and said first and second gate electrodes.
Claim 6
Dependent Claim
44 words
The device according to claim 4, wherein said pluralities of first, second and third regions are disposed essentially parallel to each other and wherein a majority of said third regions are disposed in between ones of said first and ones of said second regions.
Claim 7
Dependent Claim
33 words
The device according to claim 5, wherein said plurality of electrically interconnected first gate electrodes provide a first gate and wherein said plurality of electrically interconnected second gate electrodes provide a second gate.
Claim 8
Dependent Claim
31 words
The device according to claim 6, wherein said first and second gates are further respectively disposed over portions of said semiconductive substrate adjacent to the interdigitated first and second semiconductive regions.
Claim 9
Dependent Claim
98 words
The device according to claim 7, wherein the layer of insulating material is provided by gate oxide, wherein an active region of said first gate is defined where said first gate electrodes are disposed over gate oxide between said first and third semiconductive regions, wherein an active region of said second gate is defined wherein said second gate electrodes are disposed over gate oxide between said second and third semiconductive regions and wherein the active regions of said first and second gates are disposed along a major portion of the lengths of said first and second regions, respectively.
Claim 10
Dependent Claim
39 words
The device according to claim 5, wherein each of said first regions is disposed adjacent to differing ones of said third regions and wherein each of said second regions is disposed adjacent to differing ones of said third regions.
Claim 11
Dependent Claim
22 words
The complementary transistor pair according to claim 4, wherein said first, second and third semiconductive regions are of the P conductivity type.
Claim 12
Dependent Claim
57 words
The complementary transistor pair according to claim 10, wherein said third semiconductive regions form the source electrodes for two field effect transistors and wherein said first semiconductive regions from the drain electrode of one of said field effect transistors and wherein said second semiconductive regions form the drain electrode of the other of said field effect transistors.
Claim 13
Dependent Claim
57 words
The complementary transistor pair according to claim 10, wherein said third semiconductive regions form the drain electrodes of two field effect transistors and wherein said first semiconductive regions form the source electrode of one of said field effect transistors and wherein said second semiconductive regions form the source electrode of the other of said field effect transistors.
Claim 14
Dependent Claim
170 words
The complementary pair semiconductive device comprising: (a) a semiconductive substrate of semiconductive material selected from intrinsic or one conductivity type semiconductive material; (b) a plurality of semiconductive regions in said substrate, each of said semiconductive regions forming an elongated area of opposite conductivity type in the surface of said semiconductive substrate, the major axes thereof being essentially parallel; (c) first means for interconnecting every other one of said semiconductive regions to form a first electrode of said complementary pair semiconductive device; (d) second means for interconnecting alternating ones of said semiconductive regions not interconnected by said first means for forming a second electrode of said complementary pair semiconductor device; (e) third means for interconnecting semiconductive regions not interconnected by either of said first or second means for forming a third electrode of said complementary pair semiconductive device; and (f) gate means for forming a first gate associated with said semiconductive regions interconnected by said second means and a second gate associated with said semiconductive regions interconnected by said third means.
Claim 15
Dependent Claim
170 words
The complementary pair semiconductive device comprising: (a) a semiconductive substrate of semiconductive material selected from intrinsic or one conductivity type semiconductive material; (b) a plurality of semiconductive regions in said substrate, each of said semiconductive regions forming an elongated area of opposite conductivity type in the surface of said semiconductive substrate, the major axes thereof being essentially parallel; (c) first means for interconnecting every other one of said semiconductive regions to form a first electrode of said complementary pair semiconductive device; (d) second means for interconnecting alternating ones of said semiconductive regions not interconnected by said first means for forming a second electrode of said complementary pair semiconductor device; (e) third means for interconnecting semiconductive regions not interconnected by either of said first or second means for forming a third electrode of said complementary pair semiconductive device; and (f) gate means for forming a first gate associated with said semiconductive regions interconnected by said second means and a second gate associated with said semiconductive regions interconnected by said third means.
Claim 16
Dependent Claim
43 words
The complementary pair semiconductive device according to claim 13, wherein said first electrode is a common source electrode for a complementary field effect transistor pair and wherein said second and third electrodes are the drain electrodes of said complementary field effect transistor pair.
Claim 17
Dependent Claim
43 words
The complementary pair semiconductor device according to claim 13, wherein said first electrode is a common drain electrode for a complementary field effect transistor pair and wherein said second and third electrodes are the source electrodes of said complementary field effect transistor pair.
References Cited (Backward Citations)
US3665423A
Cited
US3813586A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-04-10 | 1981-10-10 | 1982-04-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-04-10 | 1985-10-10 | 1986-04-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-04-10 | 1989-10-10 | 1990-04-11 | $7700.00 | Window Closed / Lapsed |