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US4080660A
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Digital signal time scale inversion
Assignee: Advanced Micro Devices Inc
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Filing: 1977-02-03
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Granted: 1978-03-21
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Expires: 1997-02-03
Abstract
Abstract A system for digital signal processing, including a random access memory (RAM) accessed by counters and used for storing and shifting signals in a convolver, correlator, matched filter or multiplier. An input signal and a reference signal are applied from opposite ends of the device such that the signals scan past each other at a relative velocity with respect to each other for obtaining either the convolution or correlation function of signals. The RAM operates as a shift register delay line and provides time scale inversion of signals when desired.
Inventors
- 👤 James Nickolas Constant
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 05:45
CPC Classifications
G; G06; G06F; G06F17/00; G06F17/10; G06F17/15
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
120 words
In a system for the digital time scale inversion of signals, the combination of: digital delay means having a random access memory for storing signals in a first time sequence, said memory having storage locations for N words; an address counter connected to said memory for addressing the N storage locations in a sampling interval providing N outputs from the memory in a second time sequence, with said second time sequence from the output of said memory being one of the time sequence or time-reverse sequence of said first time sequence; and clock means connected to said memory and to said address counter for controlling timing operations of said memory, including means for shifting said memory afer each sampling interval.
Claim 2
Dependent Claim
120 words
In a system for the digital time scale inversion of signals, the combination of: digital delay means having a random access memory for storing signals in a first time sequence, said memory having storage locations for N words; an address counter connected to said memory for addressing the N storage locations in a sampling interval providing N outputs from the memory in a second time sequence, with said second time sequence from the output of said memory being one of the time sequence or time-reverse sequence of said first time sequence; and clock means connected to said memory and to said address counter for controlling timing operations of said memory, including means for shifting said memory afer each sampling interval.
Claim 3
Dependent Claim
16 words
The system of claim 1 wherein said memory includes one of a TTL, CCD, and ECL.
Claim 4
Dependent Claim
14 words
The system of claim 1 wherein said random access memory comprises a DELTIC circuit.
Claim 5
Independent Claim
91 words
A method for the digital implementation of signal time scale inversion, including the steps of: storing signals in a first time sequence in a random access memory having storage locations for N words; addressing storage locations of the memory in a sampling interval providing N outputs from the memory in a second time sequence, with said second time sequence from the output of said memory having one of the time sequence or time-reverse sequence of said first time sequence; and shifting the signal in the first memory after each sampling interval.
Claim 6
Independent Claim
91 words
A method for the digital implementation of signal time scale inversion, including the steps of: storing signals in a first time sequence in a random access memory having storage locations for N words; addressing storage locations of the memory in a sampling interval providing N outputs from the memory in a second time sequence, with said second time sequence from the output of said memory having one of the time sequence or time-reverse sequence of said first time sequence; and shifting the signal in the first memory after each sampling interval.
Claim 7
Dependent Claim
18 words
The method of claim 4 including storing the signal in a random access memory comprising a DELTIC circuit.
References Cited (Backward Citations)
US3748451A
Cited
US3774019A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-20 | 1981-09-19 | 1982-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-20 | 1985-09-19 | 1986-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-20 | 1989-09-19 | 1990-03-21 | $7700.00 | Window Closed / Lapsed |