Patent US4079505A successfully refreshed from Google Patents.
US4079505A
Expired / Lapsed
US
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Method for manufacturing a transistor
Assignee: Fujitsu Ltd
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Filing: 1976-01-21
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Granted: 1978-03-21
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Expires: 1996-01-21
Abstract
Abstract Method of manufacturing a transistor which includes an emitter pattern and a base pattern and provides a predetermined current amplification factor, and said method includes a step of measuring a current amplification factor of a monitor transistor during the manufacturing process, the characteristic feature of said method includes the steps of forming a monitor transistor pattern providing the same amplification factor as the semi-conductor device to be manufactured, providing additional portions to an emitter pattern and a base pattern of said monitor transistor pattern, contacting a probe of the measuring apparatus to said additional portions and effecting the measurement of the amplification factor of the monitor transistor.
Inventors
- 👤 Yutaka Hirano
- 👤 Takayuki Hasegawa
- 👤 Minoru Matsumoto
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 18:10
CPC Classifications
H; H10; H10P; H10P74/00; H10P74/27; H10P74/277; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/133; Y; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49004
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
273 words
In a method of producing a specified transistor having a predetermined very narrow emitter region pattern and a very narrow base region pattern with which it is impossible to make satisfactory contact by test probes of a measuring instrument because the contact regions of said probes are too large relative to the sizes of said emitter and base region patterns, the steps of: (a) producing a monitor pattern transistor having essentially the same predetermined very narrow emitter region pattern and very narrow base region pattern as said specified transistor, forming an additional emitter portion and an additional base portion on said monitor transistor, said portions being of a size that enables the contact regions of said test probes to make satisfactory contact therewith and being formed so as not to substantially affect the direct current characteristics of said monitor pattern transistor, the production of said monitor pattern transistor including the step of simultaneously subjecting said monitor pattern transistor and said specified transistor to the same diffusion process, (b) bringing the contact regions of said test probes respectively into direct contact with said additional portions of said monitor pattern transistor to measure whether said latter transistor conforms to predetermined direct current specifications, (c) continuing the simultaneous diffusion of the emitter regions plus subsequent direct current measuring if the direct current characteristics of said monitor pattern transistor does not conform to said predetermined direct current specifications, and (d) then attaching electrodes respectively to the emitter and base regions of said specified transistor after said test instrument indicates that the measured direct current characteristic of said monitor pattern transistor conforms to said predetermined direct current specifications.
Claim 2
Dependent Claim
273 words
In a method of producing a specified transistor having a predetermined very narrow emitter region pattern and a very narrow base region pattern with which it is impossible to make satisfactory contact by test probes of a measuring instrument because the contact regions of said probes are too large relative to the sizes of said emitter and base region patterns, the steps of: (a) producing a monitor pattern transistor having essentially the same predetermined very narrow emitter region pattern and very narrow base region pattern as said specified transistor, forming an additional emitter portion and an additional base portion on said monitor transistor, said portions being of a size that enables the contact regions of said test probes to make satisfactory contact therewith and being formed so as not to substantially affect the direct current characteristics of said monitor pattern transistor, the production of said monitor pattern transistor including the step of simultaneously subjecting said monitor pattern transistor and said specified transistor to the same diffusion process, (b) bringing the contact regions of said test probes respectively into direct contact with said additional portions of said monitor pattern transistor to measure whether said latter transistor conforms to predetermined direct current specifications, (c) continuing the simultaneous diffusion of the emitter regions plus subsequent direct current measuring if the direct current characteristics of said monitor pattern transistor does not conform to said predetermined direct current specifications, and (d) then attaching electrodes respectively to the emitter and base regions of said specified transistor after said test instrument indicates that the measured direct current characteristic of said monitor pattern transistor conforms to said predetermined direct current specifications.
Claim 3
Dependent Claim
25 words
In the method according to claim 1 wherein in step(a), said monitor pattern transistor and said specified transistor are produced on the same semiconductor substrate.
Claim 4
Dependent Claim
29 words
In the method according to claim 1 wherein said additional base and emitter portions of said monitor pattern transistor are respectively connected to said base and emitter regions thereof.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-20 | 1981-09-19 | 1982-03-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-20 | 1985-09-19 | 1986-03-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-20 | 1989-09-19 | 1990-03-21 | $7700.00 | Window Closed / Lapsed |