Method and apparatus to test address formulation in an advanced computer system

Claim 1

In a large scale data processing system including a segmented main memory with restricted access enforced by descriptor referenced entry, a hardware implemented instruction for testing address formulation, said hardware comprising: (a) first register means for storing a plurality of descriptors; (b) second register means for storing one descriptor; (c) first selection means connected to the first and the second register means, responsive to a selection bit of the instruction, for selecting the first register means when the selection bit is in a first state and for selecting the second register means when the selection bit is in a second state; (d) second selection means responsive to a plurality of bits in an address field portion of the instruction for selecting a one of the plurality of descriptors in the first register means when the selection bit of the instruction is in the first state and selecting the descriptor in the second register means when the selection bit is in the second state; (e) first buffer means connected to said first selection means for latching the data contained in the descriptor selected; (f) second buffer means for latching a working space number selected by a first plurality of bits of the descriptor; (g) third buffer means for latching a page number and offset generated by a second plurality of descriptor bits and an address relative to the address field of the instruction; (h) fourth buffer means for holding a real address derived, in part, from the working space number, page number, and offset; (i) first bus means connected to the first buffer means and responsive to a first store instruction for storing the contents of the first buffer in main memory; (j) second bus means connected to the second, third and fourth buffer means for storing the contents of those buffers into main memory in response to a second store instruction.