Patent US4079372A successfully refreshed from Google Patents.
US4079372A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Serial to parallel converter
Assignee: United States Department of the Navy
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Filing: 1976-05-03
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Granted: 1978-03-14
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Expires: 1996-05-03
Abstract
Abstract A serial to parallel converter receives a succession of digital bits in serial form comprising discrete data formats and control formats through its input terminal, which is coupled to a data shift register and to a control shift register. When a data format is coupled into the input, a register enable circuit enables the data register to load and convert sets of changeable data bits, comprising part of the data format, to parallel form. When a control format is coupled into the input, the register enable circuit enables the control shift register to convert sets of changeable control bits, comprising part of the control format, to parallel form. One of the changeable bits in every control format immediately followed by a data format comprises an incoming data indicator. During the period that a control format containing an incoming data indicator is being coupled to the converter, a register selector circuit responds to the indicator by instructing the register enable circuit that the next incoming format will be a data format.
Inventors
- 👤 Harry J. Koenig
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-27 13:23
CPC Classifications
H; H03; H03M; H03M9/00
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
413 words
An apparatus for accepting digital information in serial form and providing digital information in parallel form, wherein said serial form digital information comprises a succession of serial form digital bits having equal time durations, and wherein some of the serial form digital bits comprise discrete data formats and other of the serial form digital bits comprise discrete control formats so that a succession of formats are coupled into the input of the apparatus, each data format being followed in the format succession by a plurality of control formats before another data format occurs, and one or more of the digital bits comprising selected control formats are incoming data indicators, each of said selected control formats being immediately followed in the format succession by a data format, said apparatus comprising: a. a data shift register means having an input terminal coupled to the input of the apparatus and having output terminals coupled to a data output of the apparatus, for serially receiving a plurality of the digital bits comprising a data format and for converting the received bits to parallel form and coupling them to the data output of the apparatus; b. a control shift register means having an input terminal coupled to the input of the apparatus and having output terminals coupled to a control output of the apparatus, for serially receiving a plurality of the digital bits comprising a control format and for converting the received bits to parallel form and coupling them to the control output of the apparatus; c. a register enable circuit means coupled to said data shift register means and also to said control shift register means for enabling said data shift register means to receive, convert and couple out a plurality of the digital bits comprising a data format, and for enabling the control shift register means to receive, convert and couple out a plurality of the digital bits comprising each control format; d. a timing means coupled to said register enable circuit means for timing the operation of said data shift register means and of said control shift register means; e. a register selector circuit means coupled to said register enable circuit means and situated to receive each of said incoming data indicators, said register selector circuit means for responding to a received incoming data indicator by instructing said register enable circuit means to enable said data shift register means to receive, convert and couple out a plurality of the digital bits comprising a data format.
Claim 2
Independent Claim
413 words
An apparatus for accepting digital information in serial form and providing digital information in parallel form, wherein said serial form digital information comprises a succession of serial form digital bits having equal time durations, and wherein some of the serial form digital bits comprise discrete data formats and other of the serial form digital bits comprise discrete control formats so that a succession of formats are coupled into the input of the apparatus, each data format being followed in the format succession by a plurality of control formats before another data format occurs, and one or more of the digital bits comprising selected control formats are incoming data indicators, each of said selected control formats being immediately followed in the format succession by a data format, said apparatus comprising: a. a data shift register means having an input terminal coupled to the input of the apparatus and having output terminals coupled to a data output of the apparatus, for serially receiving a plurality of the digital bits comprising a data format and for converting the received bits to parallel form and coupling them to the data output of the apparatus; b. a control shift register means having an input terminal coupled to the input of the apparatus and having output terminals coupled to a control output of the apparatus, for serially receiving a plurality of the digital bits comprising a control format and for converting the received bits to parallel form and coupling them to the control output of the apparatus; c. a register enable circuit means coupled to said data shift register means and also to said control shift register means for enabling said data shift register means to receive, convert and couple out a plurality of the digital bits comprising a data format, and for enabling the control shift register means to receive, convert and couple out a plurality of the digital bits comprising each control format; d. a timing means coupled to said register enable circuit means for timing the operation of said data shift register means and of said control shift register means; e. a register selector circuit means coupled to said register enable circuit means and situated to receive each of said incoming data indicators, said register selector circuit means for responding to a received incoming data indicator by instructing said register enable circuit means to enable said data shift register means to receive, convert and couple out a plurality of the digital bits comprising a data format.
Claim 3
Dependent Claim
22 words
The apparatus of claim 1 wherein said register selector circuit means has an input operably coupled to said control shift register means.
Claim 4
Independent Claim
511 words
An apparatus for accepting digital information in serial form and providing digital information in parallel form, wherein said serial form digital information comprises a succession of serial form digital bits having equal time durations, and wherein some of the serial form digital bits comprise discrete data formats and other of the serial form digital bits comprise discrete control formats so that a succession of formats is coupled into the input of the apparatus, each data format being followed in the format succession by a plurality of control formats before another data format occurs, and one or more of the digital bits comprising selected control formats are incoming data indicators, each of said selected control formats being immediately followed in the format succession by a data format, said apparatus comprising: a. a data shift register means having an input terminal coupled to the input of the apparatus and having output terminals coupled to a data output of the apparatus, for serially receiving a plurality of the digital bits comprising a data format and for converting the received digital bits to parallel form and coupling them to the data output of the apparatus during the time period that the bits comprising the data format are being coupled into the apparatus; b. a control shift register means having an input terminal coupled to the input of the apparatus and having output terminals coupled to a control output of the apparatus, for serially receiving a plurality of the digital bits comprising a control format and for converting the received bits to parallel form and coupling them to the control output of the apparatus during the time period that the digital bits comprising the control format are being coupled into the apparatus; c. a register enable circuit means coupled to said data shift register means and also to said control shift register means for enabling said data shift register means to receive, convert and couple out a plurality of the digital bits comprising a data format during the time period that the bits comprising the data format are being coupled into the apparatus and for enabling the control shift register means to receive, convert and couple out a plurality of the digital bits comprising a control format during the time period that the bits of the control format are being coupled into the apparatus; d. a timing means coupled to said register enable circuit means for timing the operation of said data shift register means and of said control shift register means; e. a register selector circuit means coupled to said register enable circuit means and situated to receive each of said incoming data indicators, said register selector means for responding to a received incoming data indicator during the time period that the digital bits comprising the selected control format containing the indicator are being coupled into the converter, by instructing said register enable circuit means to enable said data shift register means to receive, convert and couple out a plurality of the digital bits comprising the data format immediately following the said selected control format.
Claim 5
Independent Claim
511 words
An apparatus for accepting digital information in serial form and providing digital information in parallel form, wherein said serial form digital information comprises a succession of serial form digital bits having equal time durations, and wherein some of the serial form digital bits comprise discrete data formats and other of the serial form digital bits comprise discrete control formats so that a succession of formats is coupled into the input of the apparatus, each data format being followed in the format succession by a plurality of control formats before another data format occurs, and one or more of the digital bits comprising selected control formats are incoming data indicators, each of said selected control formats being immediately followed in the format succession by a data format, said apparatus comprising: a. a data shift register means having an input terminal coupled to the input of the apparatus and having output terminals coupled to a data output of the apparatus, for serially receiving a plurality of the digital bits comprising a data format and for converting the received digital bits to parallel form and coupling them to the data output of the apparatus during the time period that the bits comprising the data format are being coupled into the apparatus; b. a control shift register means having an input terminal coupled to the input of the apparatus and having output terminals coupled to a control output of the apparatus, for serially receiving a plurality of the digital bits comprising a control format and for converting the received bits to parallel form and coupling them to the control output of the apparatus during the time period that the digital bits comprising the control format are being coupled into the apparatus; c. a register enable circuit means coupled to said data shift register means and also to said control shift register means for enabling said data shift register means to receive, convert and couple out a plurality of the digital bits comprising a data format during the time period that the bits comprising the data format are being coupled into the apparatus and for enabling the control shift register means to receive, convert and couple out a plurality of the digital bits comprising a control format during the time period that the bits of the control format are being coupled into the apparatus; d. a timing means coupled to said register enable circuit means for timing the operation of said data shift register means and of said control shift register means; e. a register selector circuit means coupled to said register enable circuit means and situated to receive each of said incoming data indicators, said register selector means for responding to a received incoming data indicator during the time period that the digital bits comprising the selected control format containing the indicator are being coupled into the converter, by instructing said register enable circuit means to enable said data shift register means to receive, convert and couple out a plurality of the digital bits comprising the data format immediately following the said selected control format.
Claim 6
Dependent Claim
22 words
The apparatus of claim 3 wherein said register selector circuit means has an input operably coupled to said control shift register means.
Claim 7
Dependent Claim
96 words
The apparatus of claim 3 wherein said data shift register means and said control shift register means each comprises a serial to parallel shift register means having a single input terminal, a plurality of output terminals, a clock terminal and a clear terminal, each of said shift register means being enabled to receive digital bits through its input terminal in serial form and to couple the received bits out of its output terminals in parallel form only when clock pulses are coupled to its clock terminal and its clear terminal is at a specified logic state.
Claim 8
Dependent Claim
57 words
The apparatus of claim 5 wherein said timing means comprises a clock providing periodic symmetrical clock pulses, wherein each of said clock pulses has the same time duration as each of said serial form digital bits, and wherein each of said serial form digital bits is coupled into said apparatus synchronously with one of said clock pulses.
Claim 9
Dependent Claim
26 words
The apparatus of claim 6 wherein said register enable circuit means and said register selector circuit means each comprises a network of interconnected logic circuit components.
Claim 10
Dependent Claim
90 words
The apparatus of claim 7 wherein each of said data formats is comprised of an equal number of digital bits, some of the bits of each data format comprising a set of changeable data bits and other bits of each data format comprising a data conversion signal, and wherein each of said control formats is comprised of an equal number of digital bits, some of the bits of each control format comprising a set of changeable control bits and other bits of each control format comprising a control conversion signal.
Claim 11
Dependent Claim
105 words
The apparatus of claim 8 wherein one or more of the said logic circuit components of the register enable circuit means is responsive to the said data conversion signal of each data format and to the said control conversion signal of each control format for enabling the data shift register means to receive, convert and couple out only the digital bits of each data format which comprise the said set of changeable data bits, and for enabling the control shift register means to receive, convert and couple out, only the digital bits of each control format which comprise the said sets of changeable control bits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-13 | 1981-09-12 | 1982-03-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-13 | 1985-09-12 | 1986-03-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-13 | 1989-09-12 | 1990-03-14 | $7700.00 | Window Closed / Lapsed |