US4078233A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Analog to digital converter circuit with gain ranging feedback
Assignee: Individual
•
Filing: 1975-08-29
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Granted: 1978-03-07
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Expires: 1995-08-29
Abstract
Abstract An acoustical testing system is described wherein a stabilized and calibrated audio sound generator is used to drive a device to be tested with the output of the device being processed by circuit means that are automatically self-adjusting thereby resulting in digital readouts of the device's output amplitude and purity.
Inventors
- 👤 George Joseph Frye
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 23:41
CPC Classifications
G; G01; G01R; G01R23/00; G01R23/16; G01R23/20; G01H; G01H3/00; G01H3/10; G01H3/12; H; H04; H04R; H04R29/00; H04R29/001; H04R25/00; H04R25/30
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
302 words
An analog to digital converter circuit comprising: calibrated AC amplifier means including input circuit means having input signal means applied thereto, gain switching means which can be switched in 10 dB increments and a plurality of output circuit means; detector means connected to one of said plurality of output circuit means of said calibrated AC amplifier means for providing a fast-varying DC signal; first comparator means connected to said detector means and providing switching signals according to said fast-varying DC signal and having an operating range of greater than 10 dB; first counter means connected to said first comparator means for receiving said switching signals and providing according thereto gain-switching signals to said gain-switching means for incrementally controlling in 10 dB increments the gain of said calibrated AC amplifier means and providing digital output signals therefrom; integrator circuit means connected to said detector means for smoothing fluctuations of said fast-varying DC signal; second comparator means connected to said integrator circuit means for providing control signals; second counter means connected to said second comparator means for receiving said control signals; feedback means connected between said second counter means and said second comparator means for setting said second counter means at a condition corresponding to the DC level of the output of said integrator circuit means such that the number provided by said second counter means has a logarithmic relation to the smoothed DC signal; third comparator means for examining the level of said smoothed DC signal and providing correction control signals; adder circuit means receiving said correction control signals and said digital output signals to provide corrected digital signals; and readout means receiving said corrected digital signals from adder means for providing most significant digit readout information and also being connected to said second counter means for providing least significant digit readout information.
Claim 2
Dependent Claim
302 words
An analog to digital converter circuit comprising: calibrated AC amplifier means including input circuit means having input signal means applied thereto, gain switching means which can be switched in 10 dB increments and a plurality of output circuit means; detector means connected to one of said plurality of output circuit means of said calibrated AC amplifier means for providing a fast-varying DC signal; first comparator means connected to said detector means and providing switching signals according to said fast-varying DC signal and having an operating range of greater than 10 dB; first counter means connected to said first comparator means for receiving said switching signals and providing according thereto gain-switching signals to said gain-switching means for incrementally controlling in 10 dB increments the gain of said calibrated AC amplifier means and providing digital output signals therefrom; integrator circuit means connected to said detector means for smoothing fluctuations of said fast-varying DC signal; second comparator means connected to said integrator circuit means for providing control signals; second counter means connected to said second comparator means for receiving said control signals; feedback means connected between said second counter means and said second comparator means for setting said second counter means at a condition corresponding to the DC level of the output of said integrator circuit means such that the number provided by said second counter means has a logarithmic relation to the smoothed DC signal; third comparator means for examining the level of said smoothed DC signal and providing correction control signals; adder circuit means receiving said correction control signals and said digital output signals to provide corrected digital signals; and readout means receiving said corrected digital signals from adder means for providing most significant digit readout information and also being connected to said second counter means for providing least significant digit readout information.
Claim 3
Dependent Claim
26 words
An analog to digital converter circuit according to claim 1 wherein said detector means includes an operational averaging detector circuit for averaging the varying output signals.
Claim 4
Dependent Claim
42 words
An analog to digital converter circuit according to claim 1 wherein said first counter means comprises BCD up-down counter means and binary to decimal converter circuit means for providing said gain-switching signals to said gain-switching means of said calibrated AC amplifier means.
Claim 5
Dependent Claim
19 words
An analog to digital converter circuit according to claim 1 wherein said second counter means comprises BCD counter means.
Claim 6
Dependent Claim
50 words
An analog to digital converter circuit according to claim 1 wherein said feedback means comprises binary to decimal converter circuit means, reference voltage means and resistor network means connected to the output of said binary to decimal converter circuit means for providing a comparison signal to said second comparator means.
Claim 7
Dependent Claim
36 words
An analog to digital converter circuit according to claim 1 wherein said readout means comprises BCD to readout decoder means and digital readout devices for displaying the states of said corrected first and second counter means.
Claim 8
Dependent Claim
20 words
An analog to digital converter circuit according to claim 6 wherein said readout decoder means includes adder said circuit means.
References Cited (Backward Citations)
US3675238A
Cited
US3613111A
Cited
US3683367A
Cited
US3662380A
Cited
US3685047A
Cited
US3790886A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-03-06 | 1981-09-05 | 1982-03-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-03-06 | 1985-09-05 | 1986-03-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-03-06 | 1989-09-05 | 1990-03-07 | $7700.00 | Window Closed / Lapsed |