Plasma display drive circuit and method

Claim 1

Apparatus for driving a plasma display panel of a type having a plurality of drive electrodes comprising a first group and a second group of drive electrodes in generally orthogonal relationship to said first group in matrix arrangement and in which orthogonal pairs of said drive electrodes uniquely specify all display elements in the panel, said apparatus comprising: selection control logic apparatus for producing selection signals for selectively addressing predetermined display elements, first sustain drive apparatus for said first group of drive electrodes comprising switches for selectively applying either a sustain amplitude voltage or a dual-on-state erase amplitude voltage to a first output and switches for selectively applying either a write amplitude voltage or a ground return voltage to a second output, second sustain drive apparatus for said second group of drive electrodes comprising switches for selectively applying either a sustain amplitude voltage or a dual-on-state erase amplitude voltage to a second output and switches for selectively applying either a write amplitude voltage or a ground return voltage to a second output, means including a fast recovery diode, for connecting each drive electrode of said first group to said second output of said first sustain drive apparatus, means including a fast recovery diode, for connecting each drive electrode of said second group to said second output of said second sustain drive apparatus, first means, including selection drivers and fast recovery diodes in matrix interconnection, for selectively connecting each drive electrode of said first group to said first output of said first sustain drive apparatus, second means, including selection drivers and fast recovery diodes in matrix interconnection, for selectively connecting each drive electrode of said second group to said first output of said second sustain drive apparatus, a plurality of charge storage diodes, at least one connected to each drive electrode of said first group and of said second group, a plurality of first clamp bus selection means for matrix interconnection to said charge storage diodes connected to the drive electrodes of said first group, each of said means being connected to at least two of said charge storage diodes, and wherein each of said clamp bus selection means comprises a charge storage diode and current limiting resistor connected in series with a low voltage clamp connected to the junction of said charge storage diode and resistor. a plurality of second clamp bus selection means for matrix interconnection to said charge storage diodes connected to the drive electrodes of said second group; each of said means being connected to at least two of said charge storage diodes and wherein each of said clamp bus selection means comprises a charge storage diode and current limiting resistor connected in series with a low voltage clamp connected to the junction of said charge storage diode and resistor, a first high voltage selection pulse circuit means, connected to each of said current limiting resistors of said first clamp bus selection means, said selection pulse circuit means being selectively operable to have as an output a write amplitude voltage, a ground return voltage, or a sustain amplitude voltage, and a second high voltage selection pulse circuit means, connected to each of said current limiting resistors of said second clamp bus selection means, said selection pulse circuit means being selectively operable to have as an output a write amplitude voltage, a ground return voltage, selective erase amplitude voltage, or a sustain amplitude voltage.