Patent US4075694A successfully refreshed from Google Patents.
US4075694A
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Apparatus in connection with a computer memory for enabling transportation of an empty memory field from one side to the other of an adjacent data field while the computer is operative
Assignee: Telefonaktiebolaget LM Ericsson AB
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Filing: 1976-10-04
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Granted: 1978-02-21
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Expires: 1996-10-04
Abstract
Abstract Apparatus is provided in connection with a computer memory for enabling a step by step transportation of an empty memory field containing a number of empty memory words from one side to the other of an adjacent data field containing a number of occupied memory words, while the computer is operative, by relocating the data field in such a manner that the information stored in each successive memory word adjacent to one border of the empty memory field is transferred to an empty memory word on the other border of the empty memory field, the latter field thus dividing the data field into two field portions which share said number of occupied memory words during the transportation. Incoming addresses, referring to a continuous area representing a data field being transferred, are converted so that the addresses instead refer to the two field portions. The continuous area is preferably identical with the relocated data field in one of its extreme positions, i.e. either the original position or the final position. By means of comparators the incoming addresses are compared with certain of the border addresses which delimit the field portions, thus determining whether or not the incoming address must be modified. When modification is to be made the address is incremented by an amount corresponding to the size of the empty memory field.
Inventors
- 👤 Ernst Enoch Ericsson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 06:14
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
358 words
In apparatus for use in a computer system having an addressable computer memory for enabling a step by step transportation of an empty memory field containing a number of empty memory words from one side to the other of an adjacent data field containing a number of occupied memory words, while the computer is operative, by relocating the data field in such a manner that the information stored in each successive memory word adjacent to one border of the empty memory field is transferred to an empty memory word on the other border of the empty memory field, the latter field thus dividing the data field into two field portions which share said number of occupied memory words during the transportation, an address modification unit for modifying of incoming addresses concerning a data field in the process of being relocated in order for the addresses to become related to said two field portions, each having two limit addresses, whereas having been related to one continuous area with two limit addresses, said continuous area being chosen such that one of said field portions is enclosed by the continuous area and shares one of its limit addresses with the latter area, said modification unit comprising comparator means for comparing said incoming addresses with that address in said empty memory field which adjoins to said one of said field portions and with a reference address which, in order to include all incoming addresses to be modified but exclude addresses relating to memory field not being concerned with said relocation, is allocated any chosen address in the address range starting with the other limit address of said continuous area and including the extreme border of the other of said field portions, and logic circuits responsive to output signals from said comparators for incrementing the incoming address by an address distance corresponding to said number of empty memory words when said output signals indicate that said incoming address falls within a range delimited by and including on the one hand said address in said empty memory field which adjoins said one of said field portions and on the other hand said reference address.
Claim 2
Dependent Claim
358 words
In apparatus for use in a computer system having an addressable computer memory for enabling a step by step transportation of an empty memory field containing a number of empty memory words from one side to the other of an adjacent data field containing a number of occupied memory words, while the computer is operative, by relocating the data field in such a manner that the information stored in each successive memory word adjacent to one border of the empty memory field is transferred to an empty memory word on the other border of the empty memory field, the latter field thus dividing the data field into two field portions which share said number of occupied memory words during the transportation, an address modification unit for modifying of incoming addresses concerning a data field in the process of being relocated in order for the addresses to become related to said two field portions, each having two limit addresses, whereas having been related to one continuous area with two limit addresses, said continuous area being chosen such that one of said field portions is enclosed by the continuous area and shares one of its limit addresses with the latter area, said modification unit comprising comparator means for comparing said incoming addresses with that address in said empty memory field which adjoins to said one of said field portions and with a reference address which, in order to include all incoming addresses to be modified but exclude addresses relating to memory field not being concerned with said relocation, is allocated any chosen address in the address range starting with the other limit address of said continuous area and including the extreme border of the other of said field portions, and logic circuits responsive to output signals from said comparators for incrementing the incoming address by an address distance corresponding to said number of empty memory words when said output signals indicate that said incoming address falls within a range delimited by and including on the one hand said address in said empty memory field which adjoins said one of said field portions and on the other hand said reference address.
Claim 3
Dependent Claim
284 words
In a computer system having a memory with a plurality of consecutively addressed memory locations divided up into three fields, a first field comprising memory locations having addresses a to b, a second field comprising memory locations having addresses b + 1 to c, and a third field comprising memory locations having addresses c + 1 to d, wherein d > c > b > a, and c - b = r, and address generating means for emitting addresses in the range from a to q, where q > d, address modification apparatus for processing addresses received in the range of from a to p to addresses in the range from a to b and from c + 1 to d for transfer to the memory where p = b + d - c, said apparatus comprising a first register means for storing the value r, second register means for storing the address d, third register means for storing the address b + 1, fourth register means for storing the address emitted by the address generating means, first comparator means for magnitude comparing the contents of said third and fourth registers, second comparator means for magnitude comparing the contents of said second and fourth registers, adder means for adding the contents of said first and fourth registers, and logic means responsive to said first and second comparator means for transmitting the address stored in said fourth register to the memory when the address stored in said fourth register is less than the address stored in said third register or greater than the address stored in said third register and for all other cases transferring to the memory the sum formed by said adder means.
Claim 4
Dependent Claim
284 words
In a computer system having a memory with a plurality of consecutively addressed memory locations divided up into three fields, a first field comprising memory locations having addresses a to b, a second field comprising memory locations having addresses b + 1 to c, and a third field comprising memory locations having addresses c + 1 to d, wherein d > c > b > a, and c - b = r, and address generating means for emitting addresses in the range from a to q, where q > d, address modification apparatus for processing addresses received in the range of from a to p to addresses in the range from a to b and from c + 1 to d for transfer to the memory where p = b + d - c, said apparatus comprising a first register means for storing the value r, second register means for storing the address d, third register means for storing the address b + 1, fourth register means for storing the address emitted by the address generating means, first comparator means for magnitude comparing the contents of said third and fourth registers, second comparator means for magnitude comparing the contents of said second and fourth registers, adder means for adding the contents of said first and fourth registers, and logic means responsive to said first and second comparator means for transmitting the address stored in said fourth register to the memory when the address stored in said fourth register is less than the address stored in said third register or greater than the address stored in said third register and for all other cases transferring to the memory the sum formed by said adder means.
Claim 5
Dependent Claim
20 words
The system of claim 2 further comprising means for unit incrementing the address to be stored is said third register.
References Cited (Backward Citations)
US3228005A
Cited
US3553652A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-20 | 1981-08-22 | 1982-02-21 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-20 | 1985-08-22 | 1986-02-21 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-20 | 1989-08-22 | 1990-02-21 | $7700.00 | Window Closed / Lapsed |