US4074207A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Interference resistant phase-locked loop
Assignee: Telefonaktiebolaget LM Ericsson AB
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Filing: 1976-12-13
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Granted: 1978-02-14
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Expires: 1996-12-13
Abstract
Abstract A phase-locked loop, especially for carrier frequency generation in frequency division multiplex telecommunication systems, which is insensitive to large instantaneous phase differences appearing at the input of the phase discriminator has in its forward path the series combination of a differentiating circuit, a limiter and an integrating circuit.
Inventors
- 👤 Gunnar S. Forsberg
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:50
CPC Classifications
H; H03; H03L; H03L7/00; H03L7/06; H03L7/08; H03L7/085; H03L7/093
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
169 words
In an interference resistant phase-locked loop, particularly for carrier frequency generation in Frequency Division Multiplex telecommunication systems of the type having a voltage controlled oscillator provided with a control input and a signal output, a phase discriminator with two inputs and one output to which inputs are fed a reference signal and a feedback signal respectively, the feedback signal being derived from the output signal of the oscillator, and a low pass filter for filtering of the phase difference representing output signal from said discriminator, the improvement comprising a transmission path arranged to connect the output of the low pass filter with the control input of the oscillator, said transmission path comprising a series connection of a differentiating circuit for the differentiation of the output signal from the low pass filter, a limiter which limits the output signal from the differentiating circuit at two levels symmetrically arranged on both sides of a zero level, and an integrating circuit having an output which produces a control voltage for said oscillator.
Claim 2
Dependent Claim
169 words
In an interference resistant phase-locked loop, particularly for carrier frequency generation in Frequency Division Multiplex telecommunication systems of the type having a voltage controlled oscillator provided with a control input and a signal output, a phase discriminator with two inputs and one output to which inputs are fed a reference signal and a feedback signal respectively, the feedback signal being derived from the output signal of the oscillator, and a low pass filter for filtering of the phase difference representing output signal from said discriminator, the improvement comprising a transmission path arranged to connect the output of the low pass filter with the control input of the oscillator, said transmission path comprising a series connection of a differentiating circuit for the differentiation of the output signal from the low pass filter, a limiter which limits the output signal from the differentiating circuit at two levels symmetrically arranged on both sides of a zero level, and an integrating circuit having an output which produces a control voltage for said oscillator.
Claim 3
Dependent Claim
89 words
A phase-locked loop according to claim 1, and further comprising a summing circuit between said differentiating circuit and said limiter, said summing circuit being provided with a first and a second input and one output, said first input being connected to the output of said differentiating circuit, an amplifier, said second input being connected to the output of the phase discriminator via said amplifier, said amplifier providing constant amplification for balancing in the phase locked condition the influence of the OFF-SET voltage of the differentiating and the integrating circuits.
Claim 4
Dependent Claim
90 words
A phase-locked loop according to claim 1, and further comprising a summing circuit between said differentiating circuit and said limiter, said summing circuit being provided with a first and a second input and one output, said first input being connected to the output of said differentiating circuit, an amplifier, said second input being connected to the output of the low pass filter via said amplifier, said amplifier providing constant amplification for balancing in the phase locked condition the influence of the OFF-SET voltages of the differentiating and the integrating circuits.
Claim 5
Dependent Claim
114 words
A phase-locked loop according to claim 1, further comprising an electrically controlled break contact means between said limiter and said integrating circuit, said break contact means being provided with a first and a second main terminal and a control input said first main terminal being connected to the output of the limiter and said second main terminal being connected to the input of the integrating circuit and threshold pulse generating means connected from the output of said limiter to the control input of said break contact means for generating a control pulse of a given width whenever there is a given change in the magnitude of the signal at the output of said limiter.
Claim 6
Dependent Claim
24 words
A phase-locked loop according to claim 4 wherein said threshold pulse generating means comprises a detecting circuit connected in series with a monostable circuit.
References Cited (Backward Citations)
US3573649A
Cited
US3903482A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-13 | 1981-08-15 | 1982-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-13 | 1985-08-15 | 1986-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-13 | 1989-08-15 | 1990-02-14 | $7700.00 | Window Closed / Lapsed |