Method and switching arrangement for synchronizing oscillators of a digital telecommunication network

Claim 3

The method defined in claim 1 wherein said producing step comprises producing a control signal which is one of the sum or average of the values of said first, second and third phase difference signals.

Claim 4

The method defined in claim 1 comprising the additional step of: transmitting said second phase difference signal in pulse code modulated form to others of the network nodes in said first network.

Claim 5

Apparatus for synchronizing clock oscillators in network nodes of a first digital communication network utilizing at least one clock oscillator in a second digital communication network, comprising: clock oscillator in each network node, first phase comparator means in each network node for receiving first line clock pulse trains from other network nodes in said first network, for comparing them, respectively, with the output of said clock oscillator, and for producing first phase difference signals proportional in value, respectively, to the phase difference between each said first line clock pulse train and the output pulse train from said clock oscillator, clock pulse train and the output pulse train from said clock oscillator, second phase comparator means for receiving from at least one clock oscillator in said second network a second line clock pulse train, for comparing the phases of said second line clock pulse train and said clock oscillator output and for producing a second phase difference signal having a value proportional to the measured phase difference, means for receiving a third phase difference signal from another network node in said first network, said third phase difference signal being produced in the other network node in the same manner as said second phase difference signal, comparator means for comparing the values of said second and third phase difference signals and for producing an output signal when said second phase difference signal exceeds said third phase difference signal, inhibiting means for blocking the passage of pulses of said second line clock pulse train to said second phase comparator means responsive to said comparator output signal, the number of pulses suppressed being dependent on the value of said comparator output signal, said inhibiting means being operative until said second phase difference signal is equal to or less than said third phase difference signal, summing means for producing a control signal having a value proportional to one of the sume or mean of the values of said first and second phase difference signals and regulating means for adjusting the frequency of said clock oscillator responsive to the value of said control signal.

Claim 6

Apparatus for synchronizing clock oscillators in network nodes of a first digital communication network utilizing at least one clock oscillator in a second digital communication network, comprising: clock oscillator in each network node, first phase comparator means in each network node for receiving first line clock pulse trains from other network nodes in said first network, for comparing them, respectively, with the output of said clock oscillator, and for producing first phase difference signals proportional in value, respectively, to the phase difference between each said first line clock pulse train and the output pulse train from said clock oscillator, clock pulse train and the output pulse train from said clock oscillator, second phase comparator means for receiving from at least one clock oscillator in said second network a second line clock pulse train, for comparing the phases of said second line clock pulse train and said clock oscillator output and for producing a second phase difference signal having a value proportional to the measured phase difference, means for receiving a third phase difference signal from another network node in said first network, said third phase difference signal being produced in the other network node in the same manner as said second phase difference signal, comparator means for comparing the values of said second and third phase difference signals and for producing an output signal when said second phase difference signal exceeds said third phase difference signal, inhibiting means for blocking the passage of pulses of said second line clock pulse train to said second phase comparator means responsive to said comparator output signal, the number of pulses suppressed being dependent on the value of said comparator output signal, said inhibiting means being operative until said second phase difference signal is equal to or less than said third phase difference signal, summing means for producing a control signal having a value proportional to one of the sume or mean of the values of said first and second phase difference signals and regulating means for adjusting the frequency of said clock oscillator responsive to the value of said control signal.

Claim 7

The apparatus defined in claim 4 further comprising: And gate means having an input connected to said comparator output and an output connected to said inhibiting means, and additional comparator means for comparing said second phase difference signal and other third phase difference signals from further network nodes, outputs of said additional comparators being connected to other inputs of said AND gate means.

Claim 8

The method defined in claim 1 wherein said suppressing step increases a frequency division factor relevant to said second line clock pulse trains.

Claim 9

The method defined in claim 6 wherein said frequency division factor is repeatedly increased at a repetition rate which is smaller than the reciprocal value of a control line time constant of said first network or is larger than a maximum line frequency difference between said first network operating at a no-load condition and said second network.

Claim 10

The method defined in claim 6 wherein said increase in the frequency division factor is repeatedly increased at a rate which is reduced by one or two orders of magnitude if said first, second and third phase difference signals are sufficiently equal.