Patent US4073054A successfully refreshed from Google Patents.
US4073054A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabricating semiconductor device
Assignee: Hitachi Ltd
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Filing: 1976-08-13
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Granted: 1978-02-14
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Expires: 1996-08-13
Abstract
Abstract An improved method for forming an isolation region of electrical insulator between elements of a semiconductor device, comprising depositing an electrical insulator at a low temperature to cover one major surface of a semiconductor substrate and to fill a groove provided in this surface of the semiconductor substrate, coating the electrical insulator layer with another electrical insulator which is etched at a rate approximately equivalent to that of the former electrical insulator, so as to make the entire top surface of the electrical insulator layer parallel to the major surface of the substrate, and then applying physical etching using ions to remove the electrical insulator layers until the surface of the substrate is exposed, whereby to provide in the groove an isolation region having a satisfactory surface flatness.
Inventors
- 👤 Tadao Kaji
- 👤 Yoshio Homma
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 10:36
CPC Classifications
H; H10; H10W; H10W10/00; H10W10/10; H10W10/17; H10D; H10D62/00; H10D62/10; H10D62/113; H10P; H10P50/00; H10P50/20; H10P50/28; H10P50/282; H10P95/00; H10P95/06; H10P95/062; H10P95/064; H10W10/01; H10W10/011; H10W10/014; H10W10/0145; Y; Y10; Y10S; Y10S148/00; Y10S148/05; Y10S148/051; Y10S148/085; Y10S148/118
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
283 words
A method of fabricating a bipolar type semiconductor integrated circuit device, comprising the steps of: (a) selectively forming an embedded N + -type layer in one major surface of a substrate of P-type silicon; (b) growing an N-type epitaxial layer all over the surface of said embedded N + -type layer and said P-type silicon substrate; (c) selectively etching said N-type epitaxial layer through a mask of suitable material to provide a groove which extends into said N + -type layer; (d) depositing an SiO 2 layer by chemical vapor deposition to cover said N-type epitaxial layer and to fill said groove; (e) coating said CVD-SiO 2 layer with a layer of PIQ resin; (f) applying rf sputtering from the side of the surface of said PIQ resin layer to remove by etching said PIQ resin layer and said CVD-SiO 2 layer to leave in said groove a portion of said CVD-SiO 2 layer having a flat surface extending flush with the surface of said mask thereby providing an isolation region; (g) forming a P-type base region in said N-type epitaxial layer by diffusion; (h) forming an N + -type emitter region in said P-type base region by diffusion; (i) forming an N + -type collector contact region in the portion of said N-type epitaxial layer external to and spaced apart by said isolation region from the portion of said N-type epitaxial layer in which said P-type base region and said N + -type emitter region are formed; (j) depositing electrodes in contact with said N + -type emitter region, said P-type base region and said N + -type collector contact region respectively; and (k) sealing the resultant device with a suitable resin.
Claim 2
Independent Claim
283 words
A method of fabricating a bipolar type semiconductor integrated circuit device, comprising the steps of: (a) selectively forming an embedded N + -type layer in one major surface of a substrate of P-type silicon; (b) growing an N-type epitaxial layer all over the surface of said embedded N + -type layer and said P-type silicon substrate; (c) selectively etching said N-type epitaxial layer through a mask of suitable material to provide a groove which extends into said N + -type layer; (d) depositing an SiO 2 layer by chemical vapor deposition to cover said N-type epitaxial layer and to fill said groove; (e) coating said CVD-SiO 2 layer with a layer of PIQ resin; (f) applying rf sputtering from the side of the surface of said PIQ resin layer to remove by etching said PIQ resin layer and said CVD-SiO 2 layer to leave in said groove a portion of said CVD-SiO 2 layer having a flat surface extending flush with the surface of said mask thereby providing an isolation region; (g) forming a P-type base region in said N-type epitaxial layer by diffusion; (h) forming an N + -type emitter region in said P-type base region by diffusion; (i) forming an N + -type collector contact region in the portion of said N-type epitaxial layer external to and spaced apart by said isolation region from the portion of said N-type epitaxial layer in which said P-type base region and said N + -type emitter region are formed; (j) depositing electrodes in contact with said N + -type emitter region, said P-type base region and said N + -type collector contact region respectively; and (k) sealing the resultant device with a suitable resin.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-13 | 1981-08-15 | 1982-02-14 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-13 | 1985-08-15 | 1986-02-14 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-13 | 1989-08-15 | 1990-02-14 | $7700.00 | Window Closed / Lapsed |