US4072976A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Gate protection device for MOS circuits
Assignee: Raytheon Co
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Filing: 1976-12-28
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Granted: 1978-02-07
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Expires: 1996-12-28
Abstract
Abstract The specification describes an integrated device for the input protection of MOS circuits. It consists of an MOS capacitor formed by the thinning of a section of the input gate dielectric, SiO 2 , and the thinning of an adjoining section of the gate metal, Al. An incoming pulse of static charge with high amplitude and short duration will break down the thinned dielectric of the capacitor before breaking down the relatively thick portion of the gate dielectric. Since the metal over the thin dielectric is also relatively thin, it evaporates from the vicinity of the fault by the generated Joule heat immediately following the breakdown. Thus, the breakdown is self healed and can be repeated many times without damaging the circuit.
Inventors
- 👤 Eliyahou Harari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 13:26
CPC Classifications
H; H10; H10D; H10D64/00; H10D64/20; H10D64/27; H10D64/311; H10D64/411; H10D64/511; H10D1/00; H10D1/60; H10D1/62; H10D1/66; H10D30/00; H10D30/60; H10D89/00; H10D89/60; H10D89/601; Y; Y10; Y10S; Y10S148/00; Y10S148/055
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
197 words
In an improved MOS device of the type having at least one field effect transistor with source, channel and drain regions formed in a semiconductor substrate, a metallic gate electrode and a gate dielectric layer which insulates said gate electrode from said source, gate and drain regions, source and drain electrodes connected to said source and drain regions respectively through ohmic connections, the improvement which comprises: a. a predetermined section of said gate dielectric which is relatively thin with respect to the remaining portion of said dielectric layer; b. a predetermined portion of said metallic gate electrode which is relatively thin with respect to the remaining portion of said gate electrode and is adjoining said relatively thin section of said gate dielectric whereby when an excessive voltage pulse is applied on said gate electrode it will cause a rupture in said thin dielectric region and a part of the metal of said relatively thin portion of said gate electrode will cause a temporary electrical short circuit between said gate electrode and said semiconductor substrate and said Joule heat produced in the vicinity removes said metal from said point of rupture and thus said short circuit is eliminated.
Claim 2
Dependent Claim
197 words
In an improved MOS device of the type having at least one field effect transistor with source, channel and drain regions formed in a semiconductor substrate, a metallic gate electrode and a gate dielectric layer which insulates said gate electrode from said source, gate and drain regions, source and drain electrodes connected to said source and drain regions respectively through ohmic connections, the improvement which comprises: a. a predetermined section of said gate dielectric which is relatively thin with respect to the remaining portion of said dielectric layer; b. a predetermined portion of said metallic gate electrode which is relatively thin with respect to the remaining portion of said gate electrode and is adjoining said relatively thin section of said gate dielectric whereby when an excessive voltage pulse is applied on said gate electrode it will cause a rupture in said thin dielectric region and a part of the metal of said relatively thin portion of said gate electrode will cause a temporary electrical short circuit between said gate electrode and said semiconductor substrate and said Joule heat produced in the vicinity removes said metal from said point of rupture and thus said short circuit is eliminated.
Claim 3
Dependent Claim
28 words
A device as set forth in claim 1 wherein: a. said semiconductor substrate is silicon; b. said gate electrode is silicon dioxide; c. said gate electrode is aluminum.
Claim 4
Dependent Claim
57 words
A device as set forth in claim 1 wherein: a. said relatively thin section of said gate dielectric is in the range of 50 A to 300 A thinner than the remaining portion of said gate dielectric; b. said relatively thin portion of said gate electrode has a thickness in the range of 200 to 2000 A.
Claim 5
Dependent Claim
192 words
In an improved MOS structure having an array of field effect devices each comprising source, gate and drain regions, formed in a semiconductor substrate, a gate dielectric layer, a metallic gate electrode, ohmic connections for said source and drain regions wherein said gate electrode is used as an input terminal for said MOS structure and wherein each such input is protected by an input protection device, the improvement which comprises: a. a predetermined portion of said gate dielectric lying under a portion of a metallic trace connected with said gate electrode, is relatively thin with respect to the remaining portion of said dielectric layer; b. a portion of said metallic trace connected with said gate electrode that lies over said thin gate dielectric portion is relatively thin whereby a spurious high voltage pulse causes a localized breakdown in a section of said thin dielectric portion causing metal from said metallic trace in the vicinity of the breakdown to establish a temporary short circuit between said gate electrode and said substrate which short circuit is interrupted by the subsequent evaporation of said metal by the heat generated by the breakdown of the dielectric.
Claim 6
Dependent Claim
192 words
In an improved MOS structure having an array of field effect devices each comprising source, gate and drain regions, formed in a semiconductor substrate, a gate dielectric layer, a metallic gate electrode, ohmic connections for said source and drain regions wherein said gate electrode is used as an input terminal for said MOS structure and wherein each such input is protected by an input protection device, the improvement which comprises: a. a predetermined portion of said gate dielectric lying under a portion of a metallic trace connected with said gate electrode, is relatively thin with respect to the remaining portion of said dielectric layer; b. a portion of said metallic trace connected with said gate electrode that lies over said thin gate dielectric portion is relatively thin whereby a spurious high voltage pulse causes a localized breakdown in a section of said thin dielectric portion causing metal from said metallic trace in the vicinity of the breakdown to establish a temporary short circuit between said gate electrode and said substrate which short circuit is interrupted by the subsequent evaporation of said metal by the heat generated by the breakdown of the dielectric.
Claim 7
Independent Claim
153 words
A device for protecting the input gate of an MOS structure comprising: a. a semiconductor substrate on which active regions for said MOS structure are formed including source, channel and drain regions; b. a gate dielectric region of predetermined thickness adjacent to said active regions of said substrate; c. a metallic gate electrode of predetermined thickness adjacent a portion of said gate dielectric region and spatially disposed over said channel region and parts of said source and drain regions whereby the thickness of said metallic gate electrode is selected so that when a spurious voltage pulse reaches said gate electrode and causes a rupture in a portion of said gate dielectric and the metal from the vicinity of said rupture is forced to pass through said rupture and electrically short said substrate to said gate electrode, said metal will be sufficiently thin to evaporate from the generated heat and interrupt said electrical short.
Claim 8
Independent Claim
153 words
A device for protecting the input gate of an MOS structure comprising: a. a semiconductor substrate on which active regions for said MOS structure are formed including source, channel and drain regions; b. a gate dielectric region of predetermined thickness adjacent to said active regions of said substrate; c. a metallic gate electrode of predetermined thickness adjacent a portion of said gate dielectric region and spatially disposed over said channel region and parts of said source and drain regions whereby the thickness of said metallic gate electrode is selected so that when a spurious voltage pulse reaches said gate electrode and causes a rupture in a portion of said gate dielectric and the metal from the vicinity of said rupture is forced to pass through said rupture and electrically short said substrate to said gate electrode, said metal will be sufficiently thin to evaporate from the generated heat and interrupt said electrical short.
Claim 9
Dependent Claim
149 words
A process for diverting spurious high currents from active and passive MOS devices which form MOS integrated circuits, said process including: a. providing selected overlying regions of metal and dielectric material which extend from and are equipotential with the metal and dielectric layers which form part of said MOS devices; and b. limiting the thickness of said selected metal and dielectric regions to values which are less than the respective thicknesses of the remaining extending metal and dielectric layers by predetermined amounts sufficient to produce rupture of the selected dielectric region when exposed to a spurious voltage spike and also sufficient to evaporate by Joule heat a portion of said selected metal region when the latter is shorted through the ruptured dielectric region to an underlying substrate, whereby the evaporation of said selected metal region removes the short therethrough and prepares said MOS integrated circuits for their intended operation.
Claim 10
Dependent Claim
149 words
A process for diverting spurious high currents from active and passive MOS devices which form MOS integrated circuits, said process including: a. providing selected overlying regions of metal and dielectric material which extend from and are equipotential with the metal and dielectric layers which form part of said MOS devices; and b. limiting the thickness of said selected metal and dielectric regions to values which are less than the respective thicknesses of the remaining extending metal and dielectric layers by predetermined amounts sufficient to produce rupture of the selected dielectric region when exposed to a spurious voltage spike and also sufficient to evaporate by Joule heat a portion of said selected metal region when the latter is shorted through the ruptured dielectric region to an underlying substrate, whereby the evaporation of said selected metal region removes the short therethrough and prepares said MOS integrated circuits for their intended operation.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1981-02-06 | 1981-08-08 | 1982-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1985-02-06 | 1985-08-08 | 1986-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1989-02-06 | 1989-08-08 | 1990-02-07 | $7700.00 | Window Closed / Lapsed |